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Searched refs:MPP_ALIGN (Results 1 – 25 of 90) sorted by relevance

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/OK3568_Linux_fs/external/rknpu2/examples/rknn_yolov5_demo/utils/
H A Dmpp_encoder.cpp7 #define MPP_ALIGN(x, a) (((x)+(a)-1)&~((a)-1)) macro
19 enc_params.hor_stride = MPP_ALIGN(enc_params.width, 16); in InitParams()
22 enc_params.ver_stride = (MPP_ALIGN(enc_params.height, 16)); in InitParams()
38 (MPP_ALIGN(enc_params.hor_stride, 32) >> 5) * in InitParams()
39 (MPP_ALIGN(enc_params.ver_stride, 32) >> 5) * 16 : in InitParams()
40 (MPP_ALIGN(enc_params.hor_stride, 64) >> 6) * in InitParams()
41 (MPP_ALIGN(enc_params.ver_stride, 16) >> 4) * 16; in InitParams()
47 …this->frame_size = MPP_ALIGN(enc_params.hor_stride, 64) * MPP_ALIGN(enc_params.ver_stride, 64) * 3… in InitParams()
56 …this->frame_size = MPP_ALIGN(enc_params.hor_stride, 64) * MPP_ALIGN(enc_params.ver_stride, 64) * 2; in InitParams()
72 … this->frame_size = MPP_ALIGN(enc_params.hor_stride, 64) * MPP_ALIGN(enc_params.ver_stride, 64); in InitParams()
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/OK3568_Linux_fs/external/mpp/utils/
H A Dmpp_enc_roi_utils.c193 RK_S32 mb_w = MPP_ALIGN(w, 64) / 64; in vepu54x_h265_set_roi()
194 RK_S32 mb_h = MPP_ALIGN(h, 64) / 64; in vepu54x_h265_set_roi()
226 RK_S32 mb_w = MPP_ALIGN(ctx->w, 16) / 16; in gen_vepu54x_roi()
227 RK_S32 mb_h = MPP_ALIGN(ctx->h, 16) / 16; in gen_vepu54x_roi()
228 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in gen_vepu54x_roi()
229 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in gen_vepu54x_roi()
463 RK_S32 mb_w = MPP_ALIGN(ctx->w, 16) / 16; in gen_vepu580_roi_h264()
464 RK_S32 mb_h = MPP_ALIGN(ctx->h, 16) / 16; in gen_vepu580_roi_h264()
465 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in gen_vepu580_roi_h264()
466 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in gen_vepu580_roi_h264()
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H A Dmpi_enc_utils.c41 stride = MPP_ALIGN(width, 8); in mpi_enc_width_default_stride()
45 stride = MPP_ALIGN(width, 16); in mpi_enc_width_default_stride()
51 stride = MPP_ALIGN(width, 8); in mpi_enc_width_default_stride()
55 stride = MPP_ALIGN(width, 8); in mpi_enc_width_default_stride()
68 stride = MPP_ALIGN(width, 8) * 2; in mpi_enc_width_default_stride()
73 stride = MPP_ALIGN(width, 8) * 3; in mpi_enc_width_default_stride()
82 stride = MPP_ALIGN(width, 8) * 4; in mpi_enc_width_default_stride()
921 RK_U32 mb_w_max = MPP_ALIGN(width, 16) / 16; in mpi_enc_gen_osd_data()
922 RK_U32 mb_h_max = MPP_ALIGN(height, 16) / 16; in mpi_enc_gen_osd_data()
923 RK_U32 step_x = MPP_ALIGN(mb_w_max, 8) / 8; in mpi_enc_gen_osd_data()
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/OK3568_Linux_fs/external/mpp/test/
H A Dmpi_enc_test.c154 (MPP_ALIGN(cmd->width, 16)); in test_ctx_init()
156 (MPP_ALIGN(cmd->height, 16)); in test_ctx_init()
179 (MPP_ALIGN(p->hor_stride, 32) >> 5) * in test_ctx_init()
180 (MPP_ALIGN(p->ver_stride, 32) >> 5) * 16 : in test_ctx_init()
181 (MPP_ALIGN(p->hor_stride, 64) >> 6) * in test_ctx_init()
182 (MPP_ALIGN(p->ver_stride, 16) >> 4) * 16; in test_ctx_init()
218 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 3 / 2; in test_ctx_init()
227 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 2; in test_ctx_init()
243 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64); in test_ctx_init()
247 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 4; in test_ctx_init()
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H A Dmpi_enc_mt_test.cpp165 (MPP_ALIGN(cmd->width, 16)); in mt_test_ctx_init()
167 (MPP_ALIGN(cmd->height, 16)); in mt_test_ctx_init()
224 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 3 / 2; in mt_test_ctx_init()
233 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 2; in mt_test_ctx_init()
249 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64); in mt_test_ctx_init()
253 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 4; in mt_test_ctx_init()
258 p->header_size = MPP_ALIGN(MPP_ALIGN(p->width, 16) * MPP_ALIGN(p->height, 16) / 16, SZ_4K); in mt_test_ctx_init()
817 region->x = MPP_ALIGN(p->width / 8, 16); in enc_test_input()
818 region->y = MPP_ALIGN(p->height / 8, 16); in enc_test_input()
827 region->x = MPP_ALIGN(p->width / 2, 16); in enc_test_input()
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/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu_v2.c227 RK_S32 aligned_w = MPP_ALIGN(w, 16); in h264e_vepu_buf_set_frame_size()
228 RK_S32 aligned_h = MPP_ALIGN(h, 16); in h264e_vepu_buf_set_frame_size()
256 bufs->nal_tab_size = MPP_ALIGN((bufs->mb_h + 1) * sizeof(RK_U32), 8); in h264e_vepu_buf_set_frame_size()
413 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
414 prep->size_c = hor_stride / 2 * MPP_ALIGN(prep->src_h / 2, 8); in h264e_vepu_prep_setup()
419 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
420 prep->size_c = hor_stride / 2 * MPP_ALIGN(prep->src_h / 2, 8); in h264e_vepu_prep_setup()
424 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
433 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
442 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
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/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_base.c29 return MPP_ALIGN(val, 16); in avsd_ver_align()
34 return MPP_ALIGN(val, 16); in avsd_hor_align()
39 return (2 * MPP_ALIGN(val, 16)); in avsd_len_align()
/OK3568_Linux_fs/external/mpp/mpp/vproc/rga/test/
H A Drga_test.cpp245 mpp_frame_set_hor_stride(src_frm, MPP_ALIGN(src_w, 16)); in main()
246 mpp_frame_set_ver_stride(src_frm, MPP_ALIGN(src_h, 16)); in main()
252 mpp_frame_set_hor_stride(dst_frm, MPP_ALIGN(dst_w, 16)); in main()
253 mpp_frame_set_ver_stride(dst_frm, MPP_ALIGN(dst_h, 16)); in main()
291 mpp_frame_set_hor_stride(src_frm, MPP_ALIGN(dst_w, 16) * 2); in main()
292 mpp_frame_set_ver_stride(src_frm, MPP_ALIGN(src_h, 16) / 2); in main()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/
H A Dvdpu382_com.c48 buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE); in update_size_offset()
262 RK_U32 down_scale_ver = MPP_ALIGN(ver_stride >> 1, 16); in vdpu382_setup_down_scale()
263 RK_U32 down_scale_hor = MPP_ALIGN(hor_stride >> 1, 16); in vdpu382_setup_down_scale()
279 com->reg030.y_scale_down_hor_stride = MPP_ALIGN(down_scale_hor, 16) >> 4; in vdpu382_setup_down_scale()
280 com->reg031.uv_scale_down_hor_stride = MPP_ALIGN(down_scale_hor, 16) >> 4; in vdpu382_setup_down_scale()
282 down_scale_y_offset = MPP_ALIGN(down_scale_y_offset, 16); in vdpu382_setup_down_scale()
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/common/
H A Dvepu_common.c176 if (!workaround && hor_stride != MPP_ALIGN(hor_stride, pixel_aign * pixel_size)) { in check_8_pixel_aligned()
180 MPP_ALIGN(hor_stride, pixel_aign * pixel_size)); in check_8_pixel_aligned()
207 hor_stride = MPP_ALIGN(hor_stride, 8); in get_vepu_pixel_stride()
213 hor_stride = MPP_ALIGN(hor_stride, 8); in get_vepu_pixel_stride()
226 hor_stride = MPP_ALIGN(hor_stride, 16); in get_vepu_pixel_stride()
246 hor_stride = MPP_ALIGN(hor_stride, 16); in get_vepu_pixel_stride()
266 hor_stride = MPP_ALIGN(hor_stride, 32); in get_vepu_pixel_stride()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c46 #define VDPU34X_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_CABAC_TAB_SIZE, SZ_4K))
48 #define VDPU34X_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_SPSPPS_SIZE, SZ_4K))
49 #define VDPU34X_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_RPS_SIZE, SZ_4K))
50 #define VDPU34X_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_SCALING_LIST_SIZE, SZ_4K))
326 return MPP_ALIGN(val, 16); in rkv_ver_align()
331 return MPP_ALIGN(val, 16); in rkv_hor_align()
336 return (MPP_ALIGN(val, 256) | 256); in rkv_hor_align_256_odds()
341 return (2 * MPP_ALIGN(val, 16)); in rkv_len_align()
346 return ((5 * MPP_ALIGN(val, 16)) / 2); in rkv_len_align_422()
558 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
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H A Dhal_h264d_vdpu382.c48 #define VDPU382_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU382_CABAC_TAB_SIZE, SZ_4K))
50 #define VDPU382_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU382_SPSPPS_SIZE, SZ_4K))
51 #define VDPU382_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU382_RPS_SIZE, SZ_4K))
52 #define VDPU382_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU382_SCALING_LIST_SIZE, SZ_4K))
332 return MPP_ALIGN(val, 16); in rkv_ver_align()
337 return MPP_ALIGN(val, 16); in rkv_hor_align()
342 return (MPP_ALIGN(val, 256) | 256); in rkv_hor_align_256_odds()
347 return (2 * MPP_ALIGN(val, 16)); in rkv_len_align()
352 return ((5 * MPP_ALIGN(val, 16)) / 2); in rkv_len_align_422()
567 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
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/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_vdpu382.c41 #define AVS2_RKV_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SHPH_SIZE, SZ_4K))
42 #define AVS2_RKV_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SCALIST_SIZE, SZ_4K))
84 return MPP_ALIGN(val, 16); in avs2d_ver_align()
90 return MPP_ALIGN(val, 16); in avs2d_hor_align()
95 return (2 * MPP_ALIGN(val, 16)); in avs2d_len_align()
100 return MPP_ALIGN(val, 64); in avs2d_hor_align_64()
292 width = MPP_ALIGN(width, ctu_size); in avs2d_refine_rcb_size()
298 rcb_bits = (MPP_ALIGN(width, ctu_size) + factor - 1) / factor * 24; in avs2d_refine_rcb_size()
305 rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1); in avs2d_refine_rcb_size()
413 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in fill_registers()
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H A Dhal_avs2d_rkv.c41 #define AVS2_RKV_SHPH_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SHPH_SIZE, SZ_4K))
42 #define AVS2_RKV_SCALIST_ALIGNED_SIZE (MPP_ALIGN(AVS2_RKV_SCALIST_SIZE, SZ_4K))
84 return MPP_ALIGN(val, 16); in avs2d_ver_align()
90 return MPP_ALIGN(val, 16); in avs2d_hor_align()
95 return (2 * MPP_ALIGN(val, 16)); in avs2d_len_align()
100 return MPP_ALIGN(val, 64); in avs2d_hor_align_64()
352 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in fill_registers()
458 common->reg016_str_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64; in fill_registers()
582 RK_U32 pic_w_align = MPP_ALIGN(pp->pic_width_in_luma_samples, segment_w); in set_up_colmv_buf()
583 RK_U32 pic_h_align = MPP_ALIGN(pp->pic_height_in_luma_samples, segment_h); in set_up_colmv_buf()
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/OK3568_Linux_fs/external/mpp/mpp/legacy/
H A Dvpu_api_legacy.cpp130 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
136 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 2 * MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
142 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 4 * MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
148 mpp_enc_cfg_set_s32(enc_cfg, "prep:ver_stride", MPP_ALIGN(height, 8)); in vpu_api_set_enc_cfg()
225 RK_U32 hor_stride = MPP_ALIGN(width, 16); in copy_align_raw_buffer_to_dest()
226 RK_U32 ver_stride = MPP_ALIGN(height, 8); in copy_align_raw_buffer_to_dest()
680 RK_U32 hor_stride = MPP_ALIGN(width, 16); in decode()
681 RK_U32 ver_stride = MPP_ALIGN(height, 16); in decode()
1051 RK_U32 hor_stride = MPP_ALIGN(width, 16); in encode()
1052 RK_U32 ver_stride = MPP_ALIGN(height, 16); in encode()
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/OK3568_Linux_fs/external/mpp/mpp/base/
H A Dmpp_frame.cpp238 fbc_offset = MPP_ALIGN(MPP_ALIGN(p->width, 16) * in mpp_frame_get_fbc_offset()
239 MPP_ALIGN(p->height, 16) / 16, SZ_4K); in mpp_frame_get_fbc_offset()
255 return MPP_ALIGN(p->width, 16); in mpp_frame_get_fbc_stride()
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/av1d/
H A Dhal_av1d_vdpu.c114 return MPP_ALIGN(val, 8); in rkv_ver_align()
119 return MPP_ALIGN(val, 8); in rkv_hor_align()
124 return (2 * MPP_ALIGN(val, 128)); in rkv_len_align()
129 return ((5 * MPP_ALIGN(val, 64)) / 2); in rkv_len_align_422()
153 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_base, MPP_ALIGN(sizeof(AV1CDFs)… in hal_av1d_alloc_res()
154 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_out_base, MPP_ALIGN(sizeof(AV1C… in hal_av1d_alloc_res()
156 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->film_grain_mem, MPP_ALIGN(sizeof(AV1Film… in hal_av1d_alloc_res()
157 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->global_model, MPP_ALIGN(GLOBAL_MODEL_SIZ… in hal_av1d_alloc_res()
158 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->tile_buf, MPP_ALIGN(32 * MaxTiles, 4096)… in hal_av1d_alloc_res()
174 RK_U32 pic_height = MPP_ALIGN(dxva->height, 64); in vdpu_av1d_filtermem_alloc()
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/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/common/
H A Dvepu541_common.c343 RK_S32 stride_h = MPP_ALIGN(w, 64) / 16; in vepu541_get_roi_buf_size()
344 RK_S32 stride_v = MPP_ALIGN(h, 64) / 16; in vepu541_get_roi_buf_size()
354 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu541_set_one_roi()
355 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu541_set_one_roi()
356 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu541_set_one_roi()
409 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu541_set_roi()
410 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu541_set_roi()
411 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu541_set_roi()
412 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in vepu541_set_roi()
H A Dvepu540c_common.c78 reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4; in vepu540c_set_roi()
79 reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4; in vepu540c_set_roi()
80 reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4; in vepu540c_set_roi()
81 reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4; in vepu540c_set_roi()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu580.c404 RK_S32 aligned_w = MPP_ALIGN(prep->width, alignment_w); in setup_hal_bufs()
405 RK_S32 aligned_h = MPP_ALIGN(prep->height, alignment_h) + 16; in setup_hal_bufs()
406 RK_S32 pixel_buf_fbc_hdr_size = MPP_ALIGN(aligned_w * aligned_h / 64, SZ_8K); in setup_hal_bufs()
409 RK_S32 thumb_buf_size = MPP_ALIGN(aligned_w / 64 * aligned_h / 64 * 256, SZ_8K); in setup_hal_bufs()
699 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu580_prep()
700 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu580_prep()
701 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu580_prep()
702 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu580_prep()
715 y_stride = MPP_ALIGN(prep->width, 16); in setup_vepu580_prep()
805 RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16); in vepu580_h264e_save_pass1_patch()
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/OK3568_Linux_fs/external/mpp/osal/
H A Dmpp_common.cpp112 return MPP_ALIGN(val, 16); in mpp_align_16()
117 return MPP_ALIGN(val, 64); in mpp_align_64()
/OK3568_Linux_fs/kernel/drivers/video/rockchip/mpp/
H A Dmpp_av1dec.c51 #define MPP_ALIGN(x, a) (((x)+(a)-1)&~((a)-1)) macro
504 line_size = MPP_ALIGN(MPP_ALIGN(width * pixel_width, 8) / 8, 16); in av1dec_set_l2_cache()
505 line_stride = MPP_ALIGN(MPP_ALIGN(width * pixel_width, 8) / 8, 16) >> 4; in av1dec_set_l2_cache()
518 line_size = MPP_ALIGN(MPP_ALIGN(width * pixel_width, 8) / 8, 16); in av1dec_set_l2_cache()
519 line_stride = MPP_ALIGN(MPP_ALIGN(width * pixel_width, 8) / 8, 16) >> 4; in av1dec_set_l2_cache()
589 u32 offset = MPP_ALIGN((vir_left + width + vir_right) * in av1dec_set_afbc()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_vdpu382.c39 #define PROB_SIZE_ALIGN_TO_4K MPP_ALIGN(PROB_SIZE, SZ_4K)
40 #define COUNT_SIZE_ALIGN_TO_4K MPP_ALIGN(COUNT_SIZE, SZ_4K)
41 #define MAX_SEGMAP_SIZE_ALIGN_TO_4K MPP_ALIGN(MAX_SEGMAP_SIZE, SZ_4K)
296 width = MPP_ALIGN(width, VP9_CTU_SIZE); in vp9d_refine_rcb_size()
297 height = MPP_ALIGN(height, VP9_CTU_SIZE); in vp9d_refine_rcb_size()
300 rcb_bits = MPP_ALIGN(width, 64) * 232 + ext_align_size; in vp9d_refine_rcb_size()
307 rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1) + ext_align_size; in vp9d_refine_rcb_size()
314 rcb_bits = (MPP_ALIGN(height - 8192, 4) << 1); in vp9d_refine_rcb_size()
636 RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64); in hal_vp9d_vdpu382_gen_regs()
637 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu382_gen_regs()
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H A Dhal_vp9d_vdpu34x.c39 #define PROB_SIZE_ALIGN_TO_4K MPP_ALIGN(PROB_SIZE, SZ_4K)
40 #define COUNT_SIZE_ALIGN_TO_4K MPP_ALIGN(COUNT_SIZE, SZ_4K)
41 #define MAX_SEGMAP_SIZE_ALIGN_TO_4K MPP_ALIGN(MAX_SEGMAP_SIZE, SZ_4K)
294 width = MPP_ALIGN(width, VP9_CTU_SIZE); in vp9d_refine_rcb_size()
295 height = MPP_ALIGN(height, VP9_CTU_SIZE); in vp9d_refine_rcb_size()
298 rcb_bits = MPP_ALIGN(width, 64) * 232 + ext_align_size; in vp9d_refine_rcb_size()
304 rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1) + ext_align_size; in vp9d_refine_rcb_size()
310 rcb_bits = (MPP_ALIGN(height - 8192, 4) << 1) + ext_align_size; in vp9d_refine_rcb_size()
626 RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64); in hal_vp9d_vdpu34x_gen_regs()
627 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K); in hal_vp9d_vdpu34x_gen_regs()
[all …]
/OK3568_Linux_fs/external/mpp/mpp/codec/enc/h264/
H A Dh264e_sps.c72 RK_S32 aligned_w = MPP_ALIGN(width, 16); in h264e_sps_update()
73 RK_S32 aligned_h = MPP_ALIGN(height, 16); in h264e_sps_update()
74 RK_S32 crop_right = MPP_ALIGN(width, 16) - width; in h264e_sps_update()
75 RK_S32 crop_bottom = MPP_ALIGN(height, 16) - height; in h264e_sps_update()

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