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Searched refs:MEM_CTLR (Results 1 – 3 of 3) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/x86/cpu/quark/
H A Dsmc.c63 mrc_write_mask(MEM_CTLR, PMSTS, PMSTS_DISR, PMSTS_DISR); in clear_self_refresh()
82 dtr0 = msg_port_read(MEM_CTLR, DTR0); in prog_ddr_timing_control()
83 dtr1 = msg_port_read(MEM_CTLR, DTR1); in prog_ddr_timing_control()
84 dtr2 = msg_port_read(MEM_CTLR, DTR2); in prog_ddr_timing_control()
85 dtr3 = msg_port_read(MEM_CTLR, DTR3); in prog_ddr_timing_control()
86 dtr4 = msg_port_read(MEM_CTLR, DTR4); in prog_ddr_timing_control()
172 msg_port_write(MEM_CTLR, DTR0, dtr0); in prog_ddr_timing_control()
173 msg_port_write(MEM_CTLR, DTR1, dtr1); in prog_ddr_timing_control()
174 msg_port_write(MEM_CTLR, DTR2, dtr2); in prog_ddr_timing_control()
175 msg_port_write(MEM_CTLR, DTR3, dtr3); in prog_ddr_timing_control()
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H A Dmrc_util.c83 dco = msg_port_read(MEM_CTLR, DCO); in select_mem_mgr()
85 msg_port_write(MEM_CTLR, DCO, dco); in select_mem_mgr()
97 dco = msg_port_read(MEM_CTLR, DCO); in select_hte()
99 msg_port_write(MEM_CTLR, DCO, dco); in select_hte()
112 msg_port_setup(MSG_OP_DRAM_INIT, MEM_CTLR, 0); in dram_init_command()
114 DPF(D_REGWR, "WR32 %03X %08X %08X\n", MEM_CTLR, 0, data); in dram_init_command()
122 msg_port_setup(MSG_OP_DRAM_WAKE, MEM_CTLR, 0); in dram_wake_command()
H A Dmrc_util.h45 #define MEM_CTLR 0x01 macro