Searched refs:LANE_SEQ_CTL (Results 1 – 2 of 2) sorted by relevance
201 tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val); in tegra_dc_sor_enable_lane_sequencer()203 if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL, in tegra_dc_sor_enable_lane_sequencer()572 DUMP_REG(LANE_SEQ_CTL); in dump_sor_reg()
402 #define LANE_SEQ_CTL 0x21 macro