Searched refs:EMIF_REG_WRLVLINC_INT_SHIFT (Results 1 – 2 of 2) sorted by relevance
501 #define EMIF_REG_WRLVLINC_INT_SHIFT 0 macro534 #define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \
242 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, in omap5_ddr3_leveling()