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Searched refs:CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2114 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_gfx_resume()
H A Dgfx_v7_0.c2626 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v7_0_cp_gfx_resume()
H A Dgfx_v8_0.c4296 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v8_0_cp_gfx_resume()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2724 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L macro
H A Dgfx_7_2_sh_mask.h1057 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
H A Dgfx_8_1_sh_mask.h1897 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
H A Dgfx_8_0_sh_mask.h1373 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10705 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro
H A Dgc_9_2_1_sh_mask.h11991 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro
H A Dgc_9_1_sh_mask.h12186 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro
H A Dgc_10_1_0_sh_mask.h17616 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro
H A Dgc_10_3_0_sh_mask.h15861 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro