Searched refs:CLK_PCIE_PHY1_PLL_DIV_SHIFT (Results 1 – 2 of 2) sorted by relevance
424 CLK_PCIE_PHY1_PLL_DIV_SHIFT = 6, enumerator425 CLK_PCIE_PHY1_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY1_PLL_DIV_SHIFT,
1441 div = (con & CLK_PCIE_PHY1_PLL_DIV_MASK) >> CLK_PCIE_PHY1_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()1488 ((div - 1) << CLK_PCIE_PHY1_PLL_DIV_SHIFT)); in rk3588_pciephy_set_rate()