Searched refs:CLK_PCIE_PHY0_PLL_DIV_SHIFT (Results 1 – 2 of 2) sorted by relevance
426 CLK_PCIE_PHY0_PLL_DIV_SHIFT = 0, enumerator427 CLK_PCIE_PHY0_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY0_PLL_DIV_SHIFT,
1435 div = (con & CLK_PCIE_PHY0_PLL_DIV_MASK) >> CLK_PCIE_PHY0_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()1480 ((div - 1) << CLK_PCIE_PHY0_PLL_DIV_SHIFT)); in rk3588_pciephy_set_rate()