Searched refs:CLK_CTRL_DIV0_MASK (Results 1 – 2 of 2) sorted by relevance
34 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) macro177 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_cpu_rate()232 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_dci_rate()249 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_peripheral_rate()328 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynq_clk_set_peripheral_rate()
98 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) macro355 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_cpu_rate()378 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_ddr_rate()403 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_peripheral_rate()472 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynqmp_clk_set_peripheral_rate()