Searched refs:CCSR_PLL3_SW_CLK_SEL (Results 1 – 1 of 1) sorted by relevance
256 #define CCSR_PLL3_SW_CLK_SEL BIT(0) macro275 reg |= CCSR_PLL3_SW_CLK_SEL; in mmdc_ch1_disable()285 reg &= ~CCSR_PLL3_SW_CLK_SEL; in mmdc_ch1_reenable()