Searched refs:BIT_MASK_REG_V15_3_TO_0_V1 (Results 1 – 5 of 5) sorted by relevance
3822 #define BIT_MASK_REG_V15_3_TO_0_V1 0xf macro3823 #define BIT_REG_V15_3_TO_0_V1(x) (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_…3824 … BIT_GET_REG_V15_3_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1)
5269 #define BIT_MASK_REG_V15_3_TO_0_V1 0xf macro5271 (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1)5273 (BIT_MASK_REG_V15_3_TO_0_V1 << BIT_SHIFT_REG_V15_3_TO_0_V1)5276 (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1)
5270 #define BIT_MASK_REG_V15_3_TO_0_V1 0xf macro5272 (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1)5274 (BIT_MASK_REG_V15_3_TO_0_V1 << BIT_SHIFT_REG_V15_3_TO_0_V1)5277 (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1)