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Searched refs:AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h12176 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
H A Ddce_10_0_sh_mask.h13434 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
H A Ddce_11_0_sh_mask.h13440 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
H A Ddce_11_2_sh_mask.h14056 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
H A Ddce_12_0_sh_mask.h7017 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h8152 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h7557 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h7825 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h7470 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro