Home
last modified time | relevance | path

Searched refs:AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h12175 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 macro
H A Ddce_10_0_sh_mask.h13433 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 macro
H A Ddce_11_0_sh_mask.h13439 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 macro
H A Ddce_11_2_sh_mask.h14055 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 macro
H A Ddce_12_0_sh_mask.h7020 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h8155 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK … macro
H A Ddcn_2_1_0_sh_mask.h7560 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h7828 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h7473 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK … macro