Searched refs:AR933X_SRIF_DDR_DPLL4_REG (Results 1 – 2 of 2) sorted by relevance
255 lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
1122 #define AR933X_SRIF_DDR_DPLL4_REG 0x24c macro