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| H A D | cache_helpers.S | f999faca06e8ff5d6d23a08d844c6a4ad38e3000 Tue Apr 09 13:45:34 UTC 2019 Joel Hutton <Joel.Hutton@Arm.com> Add note about erratum 814220 for A7
On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.
Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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