Searched hist:f48deced8244471128be4da20b5773d6a7a17f99 (Results 1 – 7 of 7) sorted by relevance
| /rkbin/RKBOOT/ |
| H A D | RK3568MINIALL_PCIE_EP.ini | f48deced8244471128be4da20b5773d6a7a17f99 Fri Nov 24 07:08:58 UTC 2023 Tang Yun ping <typ@rock-chips.com> rk3568: ddr: update ddrbin to v1.20
build from:
77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz
build command:
./make.sh rk3568
update feature:
1. When DDR ECC is enabled, ensure the correctness of the
ECC of the pstore segment memory after restarting.
2. Update DDR3/LPDDR3 rd/wr training pattern to improve
read and write signal margin.
3. Fixed 6GB LPDDR3/4 initialization failure problem.
4. LPDDR4/4X enable 780MHz read odt。
5. Eanble read/write vref training to improve
compatibility.(can be disable using ddrbin_tool).
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I1ef3ac7528106b937da236529d1a2f26041b5ce0
|
| H A D | RK3568MINIALL_RAMBOOT.ini | f48deced8244471128be4da20b5773d6a7a17f99 Fri Nov 24 07:08:58 UTC 2023 Tang Yun ping <typ@rock-chips.com> rk3568: ddr: update ddrbin to v1.20
build from:
77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz
build command:
./make.sh rk3568
update feature:
1. When DDR ECC is enabled, ensure the correctness of the
ECC of the pstore segment memory after restarting.
2. Update DDR3/LPDDR3 rd/wr training pattern to improve
read and write signal margin.
3. Fixed 6GB LPDDR3/4 initialization failure problem.
4. LPDDR4/4X enable 780MHz read odt。
5. Eanble read/write vref training to improve
compatibility.(can be disable using ddrbin_tool).
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I1ef3ac7528106b937da236529d1a2f26041b5ce0
|
| H A D | RK3568MINIALL_SPI_NAND.ini | f48deced8244471128be4da20b5773d6a7a17f99 Fri Nov 24 07:08:58 UTC 2023 Tang Yun ping <typ@rock-chips.com> rk3568: ddr: update ddrbin to v1.20
build from:
77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz
build command:
./make.sh rk3568
update feature:
1. When DDR ECC is enabled, ensure the correctness of the
ECC of the pstore segment memory after restarting.
2. Update DDR3/LPDDR3 rd/wr training pattern to improve
read and write signal margin.
3. Fixed 6GB LPDDR3/4 initialization failure problem.
4. LPDDR4/4X enable 780MHz read odt。
5. Eanble read/write vref training to improve
compatibility.(can be disable using ddrbin_tool).
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I1ef3ac7528106b937da236529d1a2f26041b5ce0
|
| H A D | RK3568MINIALL_NAND.ini | f48deced8244471128be4da20b5773d6a7a17f99 Fri Nov 24 07:08:58 UTC 2023 Tang Yun ping <typ@rock-chips.com> rk3568: ddr: update ddrbin to v1.20
build from:
77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz
build command:
./make.sh rk3568
update feature:
1. When DDR ECC is enabled, ensure the correctness of the
ECC of the pstore segment memory after restarting.
2. Update DDR3/LPDDR3 rd/wr training pattern to improve
read and write signal margin.
3. Fixed 6GB LPDDR3/4 initialization failure problem.
4. LPDDR4/4X enable 780MHz read odt。
5. Eanble read/write vref training to improve
compatibility.(can be disable using ddrbin_tool).
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I1ef3ac7528106b937da236529d1a2f26041b5ce0
|
| H A D | RK3568MINIALL.ini | f48deced8244471128be4da20b5773d6a7a17f99 Fri Nov 24 07:08:58 UTC 2023 Tang Yun ping <typ@rock-chips.com> rk3568: ddr: update ddrbin to v1.20
build from:
77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz
build command:
./make.sh rk3568
update feature:
1. When DDR ECC is enabled, ensure the correctness of the
ECC of the pstore segment memory after restarting.
2. Update DDR3/LPDDR3 rd/wr training pattern to improve
read and write signal margin.
3. Fixed 6GB LPDDR3/4 initialization failure problem.
4. LPDDR4/4X enable 780MHz read odt。
5. Eanble read/write vref training to improve
compatibility.(can be disable using ddrbin_tool).
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I1ef3ac7528106b937da236529d1a2f26041b5ce0
|
| /rkbin/doc/release/ |
| H A D | RK3568_EN.md | f48deced8244471128be4da20b5773d6a7a17f99 Fri Nov 24 07:08:58 UTC 2023 Tang Yun ping <typ@rock-chips.com> rk3568: ddr: update ddrbin to v1.20
build from:
77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz
build command:
./make.sh rk3568
update feature:
1. When DDR ECC is enabled, ensure the correctness of the
ECC of the pstore segment memory after restarting.
2. Update DDR3/LPDDR3 rd/wr training pattern to improve
read and write signal margin.
3. Fixed 6GB LPDDR3/4 initialization failure problem.
4. LPDDR4/4X enable 780MHz read odt。
5. Eanble read/write vref training to improve
compatibility.(can be disable using ddrbin_tool).
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I1ef3ac7528106b937da236529d1a2f26041b5ce0
|
| H A D | RK3568_CN.md | f48deced8244471128be4da20b5773d6a7a17f99 Fri Nov 24 07:08:58 UTC 2023 Tang Yun ping <typ@rock-chips.com> rk3568: ddr: update ddrbin to v1.20
build from:
77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz
build command:
./make.sh rk3568
update feature:
1. When DDR ECC is enabled, ensure the correctness of the
ECC of the pstore segment memory after restarting.
2. Update DDR3/LPDDR3 rd/wr training pattern to improve
read and write signal margin.
3. Fixed 6GB LPDDR3/4 initialization failure problem.
4. LPDDR4/4X enable 780MHz read odt。
5. Eanble read/write vref training to improve
compatibility.(can be disable using ddrbin_tool).
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I1ef3ac7528106b937da236529d1a2f26041b5ce0
|