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| H A D | RK3568MINIALL.ini | f0efa2d6fb156afb4707e0d6a32a89ee45ebebb6 Tue Dec 22 13:31:51 UTC 2020 Tang Yun ping <typ@rock-chips.com> rk3568: ddr: update ddr bin to v1.03
print info:
DDR Version V1.03 20201224
build from u-boot-ddr:
434fcab38a rk356x: ddr: ddr bin version update to v1.03 20201224
build command:
./make.sh rk3568
update feature:
ad78184260 rk356x: ddr: disable ca odt when freq smaller than 800
498c940405 rk356x: ddr: gating training logic for power saving
f1e7e8286d rk356x: ddr: fix phy 2 cs cmd switch bug
cd72792efa rk356x: ddr: msch div follow with ddr freq
3d038f9428 rk356x: ddr: fix some ddr bug
01d47d2a87 rk356x: ddr: ddr_freq match DPLL setting
30a7d012c0 rk356x: ddr: add cs2_3_ca_skew in rk3568_fsp_param
56dd70be24 rk356x: ddr: lp4x use lp4 inc file to reduce code size
7e665ae1e3 rk356x: ddr: fix bug of pucal set
e15c349125 rk356x: ddr: set diff cs rd/wr gap to 2
11d6a8467e rk356x: ddr: fix auto low power bug and en auto low power
41385de8e5 rk356x: ddr: adjust drv/odt info
400a568e95 rk356x: ddr: optimizing and fix some code bug
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I02774dfb739615f3e4653fb2638569037779bc27
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