Searched hist:e8719552a243b7e7e0d2fd3401669e68c9519170 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/lib/xlat_tables/ |
| H A D | xlat_tables_private.h | e8719552a243b7e7e0d2fd3401669e68c9519170 Tue Aug 02 08:21:41 UTC 2016 Antonio Nino Diaz <antonio.ninodiaz@arm.com> Automatically select initial xlation lookup level
Instead of hardcoding a level 1 table as the base translation level
table, let the code decide which level is the most appropriate given
the virtual address space size.
As the table granularity is 4 KB, this allows the code to select
level 0, 1 or 2 as base level for AArch64. This way, instead of
limiting the virtual address space width to 39-31 bits, widths of
48-25 bit can be used.
For AArch32, this change allows the code to select level 1 or 2
as the base translation level table and use virtual address space
width of 32-25 bits.
Also removed some unused definitions related to translation tables.
Fixes ARM-software/tf-issues#362
Change-Id: Ie3bb5d6d1a4730a26700b09827c79f37ca3cdb65
|
| H A D | xlat_tables_common.c | e8719552a243b7e7e0d2fd3401669e68c9519170 Tue Aug 02 08:21:41 UTC 2016 Antonio Nino Diaz <antonio.ninodiaz@arm.com> Automatically select initial xlation lookup level
Instead of hardcoding a level 1 table as the base translation level
table, let the code decide which level is the most appropriate given
the virtual address space size.
As the table granularity is 4 KB, this allows the code to select
level 0, 1 or 2 as base level for AArch64. This way, instead of
limiting the virtual address space width to 39-31 bits, widths of
48-25 bit can be used.
For AArch32, this change allows the code to select level 1 or 2
as the base translation level table and use virtual address space
width of 32-25 bits.
Also removed some unused definitions related to translation tables.
Fixes ARM-software/tf-issues#362
Change-Id: Ie3bb5d6d1a4730a26700b09827c79f37ca3cdb65
|
| /rk3399_ARM-atf/lib/xlat_tables/aarch32/ |
| H A D | xlat_tables.c | e8719552a243b7e7e0d2fd3401669e68c9519170 Tue Aug 02 08:21:41 UTC 2016 Antonio Nino Diaz <antonio.ninodiaz@arm.com> Automatically select initial xlation lookup level
Instead of hardcoding a level 1 table as the base translation level
table, let the code decide which level is the most appropriate given
the virtual address space size.
As the table granularity is 4 KB, this allows the code to select
level 0, 1 or 2 as base level for AArch64. This way, instead of
limiting the virtual address space width to 39-31 bits, widths of
48-25 bit can be used.
For AArch32, this change allows the code to select level 1 or 2
as the base translation level table and use virtual address space
width of 32-25 bits.
Also removed some unused definitions related to translation tables.
Fixes ARM-software/tf-issues#362
Change-Id: Ie3bb5d6d1a4730a26700b09827c79f37ca3cdb65
|
| /rk3399_ARM-atf/lib/xlat_tables/aarch64/ |
| H A D | xlat_tables.c | e8719552a243b7e7e0d2fd3401669e68c9519170 Tue Aug 02 08:21:41 UTC 2016 Antonio Nino Diaz <antonio.ninodiaz@arm.com> Automatically select initial xlation lookup level
Instead of hardcoding a level 1 table as the base translation level
table, let the code decide which level is the most appropriate given
the virtual address space size.
As the table granularity is 4 KB, this allows the code to select
level 0, 1 or 2 as base level for AArch64. This way, instead of
limiting the virtual address space width to 39-31 bits, widths of
48-25 bit can be used.
For AArch32, this change allows the code to select level 1 or 2
as the base translation level table and use virtual address space
width of 32-25 bits.
Also removed some unused definitions related to translation tables.
Fixes ARM-software/tf-issues#362
Change-Id: Ie3bb5d6d1a4730a26700b09827c79f37ca3cdb65
|