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| H A D | conf.mk | e088dff5f6f1386910e0a4e9e3cc3808f4a9b03f Thu Dec 07 15:31:15 UTC 2023 Alvin Chang <alvinga@andestech.com> riscv: virt: Enable configurations for S-mode execution
In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we
enable CFG_RISCV_SBI so that OP-TEE utilizes SBI to communicate with
other OS.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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