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H A Dci.ymld8d2e5e6389b5fa969794b19bbdbb026bf0ef996 Tue Jan 03 18:14:36 UTC 2023 Jorge Ramirez-Ortiz <jorge@foundries.io> ci: versal: program FPGA

Provide CFG_VERSAL_FPGA_DDR_ADDR to exercise this code path

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>