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H A Dversal_def.hd69bbd0e80d07d4c9008a0666e192491ddf52e43 Fri May 03 11:05:25 UTC 2019 Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> xilinx: versal: Wire silicon default setup

Add new option for serial and default clock setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a