Searched hist:"8 e85791677a334bc7ed0799b18adad91ef3c1db4" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/aarch64/ |
| H A D | cache_helpers.S | 8e85791677a334bc7ed0799b18adad91ef3c1db4 Tue Sep 02 09:47:33 UTC 2014 Soby Mathew <soby.mathew@arm.com> Add support for level specific cache maintenance operations
This patch adds level specific cache maintenance functions
to cache_helpers.S. The new functions 'dcsw_op_levelx',
where '1 <= x <= 3', allow to perform cache maintenance by
set/way for that particular level of cache. With this patch,
functions to support cache maintenance upto level 3 have
been implemented since it is the highest cache level for
most ARM SoCs.
These functions are now utilized in CPU specific power down
sequences to implement them as mandated by processor specific
technical reference manual.
Change-Id: Icd90ce6b51cff5a12863bcda01b93601417fd45c
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a53.S | 8e85791677a334bc7ed0799b18adad91ef3c1db4 Tue Sep 02 09:47:33 UTC 2014 Soby Mathew <soby.mathew@arm.com> Add support for level specific cache maintenance operations
This patch adds level specific cache maintenance functions
to cache_helpers.S. The new functions 'dcsw_op_levelx',
where '1 <= x <= 3', allow to perform cache maintenance by
set/way for that particular level of cache. With this patch,
functions to support cache maintenance upto level 3 have
been implemented since it is the highest cache level for
most ARM SoCs.
These functions are now utilized in CPU specific power down
sequences to implement them as mandated by processor specific
technical reference manual.
Change-Id: Icd90ce6b51cff5a12863bcda01b93601417fd45c
|
| H A D | cortex_a57.S | 8e85791677a334bc7ed0799b18adad91ef3c1db4 Tue Sep 02 09:47:33 UTC 2014 Soby Mathew <soby.mathew@arm.com> Add support for level specific cache maintenance operations
This patch adds level specific cache maintenance functions
to cache_helpers.S. The new functions 'dcsw_op_levelx',
where '1 <= x <= 3', allow to perform cache maintenance by
set/way for that particular level of cache. With this patch,
functions to support cache maintenance upto level 3 have
been implemented since it is the highest cache level for
most ARM SoCs.
These functions are now utilized in CPU specific power down
sequences to implement them as mandated by processor specific
technical reference manual.
Change-Id: Icd90ce6b51cff5a12863bcda01b93601417fd45c
|