Searched hist:"7 a4a07078b3d15648c1cbbd9f309b0c11da56165" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/ |
| H A D | nrd_plat_arm_def3.h | 7a4a07078b3d15648c1cbbd9f309b0c11da56165 Wed Jan 22 15:12:08 UTC 2025 AlexeiFedorov <Alexei.Fedorov@arm.com> feat(fvp): allocate L0 GPT at the top of SRAM
This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unused gaps in SRAM.
Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are
defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro.
Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
|
| /rk3399_ARM-atf/plat/arm/board/fvp/fdts/ |
| H A D | fvp_fw_config.dts | 7a4a07078b3d15648c1cbbd9f309b0c11da56165 Wed Jan 22 15:12:08 UTC 2025 AlexeiFedorov <Alexei.Fedorov@arm.com> feat(fvp): allocate L0 GPT at the top of SRAM
This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unused gaps in SRAM.
Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are
defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro.
Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
|
| /rk3399_ARM-atf/include/plat/arm/common/ |
| H A D | arm_def.h | 7a4a07078b3d15648c1cbbd9f309b0c11da56165 Wed Jan 22 15:12:08 UTC 2025 AlexeiFedorov <Alexei.Fedorov@arm.com> feat(fvp): allocate L0 GPT at the top of SRAM
This patch allocates level 0 GPT at the top of SRAM
for FVP. This helps to meet L0 GPT alignment requirements
and prevent the occurrence of possible unused gaps in SRAM.
Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are
defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro.
Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
|