Searched hist:"683 f788fa7374669724eb419a8c3e763b05bcc5c" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a53.S | 683f788fa7374669724eb419a8c3e763b05bcc5c Thu Jan 29 12:00:58 UTC 2015 Soby Mathew <soby.mathew@arm.com> Fix the Cortex-A57 reset handler register usage
The CPU specific reset handlers no longer have the freedom
of using any general purpose register because it is being invoked
by the BL3-1 entry point in addition to BL1. The Cortex-A57 CPU
specific reset handler was overwriting x20 register which was being
used by the BL3-1 entry point to save the entry point information.
This patch fixes this bug by reworking the register allocation in the
Cortex-A57 reset handler to avoid using x20. The patch also
explicitly mentions the register clobber list for each of the
callee functions invoked by the reset handler
Change-Id: I28fcff8e742aeed883eaec8f6c4ee2bd3fce30df
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| H A D | cpu_helpers.S | 683f788fa7374669724eb419a8c3e763b05bcc5c Thu Jan 29 12:00:58 UTC 2015 Soby Mathew <soby.mathew@arm.com> Fix the Cortex-A57 reset handler register usage
The CPU specific reset handlers no longer have the freedom
of using any general purpose register because it is being invoked
by the BL3-1 entry point in addition to BL1. The Cortex-A57 CPU
specific reset handler was overwriting x20 register which was being
used by the BL3-1 entry point to save the entry point information.
This patch fixes this bug by reworking the register allocation in the
Cortex-A57 reset handler to avoid using x20. The patch also
explicitly mentions the register clobber list for each of the
callee functions invoked by the reset handler
Change-Id: I28fcff8e742aeed883eaec8f6c4ee2bd3fce30df
|
| H A D | cortex_a57.S | 683f788fa7374669724eb419a8c3e763b05bcc5c Thu Jan 29 12:00:58 UTC 2015 Soby Mathew <soby.mathew@arm.com> Fix the Cortex-A57 reset handler register usage
The CPU specific reset handlers no longer have the freedom
of using any general purpose register because it is being invoked
by the BL3-1 entry point in addition to BL1. The Cortex-A57 CPU
specific reset handler was overwriting x20 register which was being
used by the BL3-1 entry point to save the entry point information.
This patch fixes this bug by reworking the register allocation in the
Cortex-A57 reset handler to avoid using x20. The patch also
explicitly mentions the register clobber list for each of the
callee functions invoked by the reset handler
Change-Id: I28fcff8e742aeed883eaec8f6c4ee2bd3fce30df
|