Searched hist:"5 de20ece38f782c8459f546a08c6a97b9e0f5bc5" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | el3_common_macros.S | 5de20ece38f782c8459f546a08c6a97b9e0f5bc5 Sun Jul 18 01:26:27 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(trf): initialize trap settings of trace filter control registers access
Trap bits of trace filter control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace filter control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRF is implemented.
2. These bits are RES0 when FEAT_TRF is not implemented and hence set
it to zero to aligns with the Arm ARM reference recommendation,
that mentions software must writes RES0 bits with all 0s.
Change-Id: I1b7abf2170ece84ee585c91cda32d22b25c0fc34
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|
| H A D | arch.h | 5de20ece38f782c8459f546a08c6a97b9e0f5bc5 Sun Jul 18 01:26:27 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(trf): initialize trap settings of trace filter control registers access
Trap bits of trace filter control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace filter control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRF is implemented.
2. These bits are RES0 when FEAT_TRF is not implemented and hence set
it to zero to aligns with the Arm ARM reference recommendation,
that mentions software must writes RES0 bits with all 0s.
Change-Id: I1b7abf2170ece84ee585c91cda32d22b25c0fc34
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | el3_common_macros.S | 5de20ece38f782c8459f546a08c6a97b9e0f5bc5 Sun Jul 18 01:26:27 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(trf): initialize trap settings of trace filter control registers access
Trap bits of trace filter control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace filter control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRF is implemented.
2. These bits are RES0 when FEAT_TRF is not implemented and hence set
it to zero to aligns with the Arm ARM reference recommendation,
that mentions software must writes RES0 bits with all 0s.
Change-Id: I1b7abf2170ece84ee585c91cda32d22b25c0fc34
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|
| H A D | arch.h | 5de20ece38f782c8459f546a08c6a97b9e0f5bc5 Sun Jul 18 01:26:27 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(trf): initialize trap settings of trace filter control registers access
Trap bits of trace filter control registers access are in
architecturally UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace filter control
registers accesses in lower ELs (EL2, EL1) in all security states
when FEAT_TRF is implemented.
2. These bits are RES0 when FEAT_TRF is not implemented and hence set
it to zero to aligns with the Arm ARM reference recommendation,
that mentions software must writes RES0 bits with all 0s.
Change-Id: I1b7abf2170ece84ee585c91cda32d22b25c0fc34
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|