Searched hist:"5 c96d2c0c5892ba3b98a021737b95f36ff3b4612" (Results 1 – 6 of 6) sorted by relevance
| /rkbin/RKBOOT/ |
| H A D | RK3308MINIALL_SPI_NAND.ini | 5c96d2c0c5892ba3b98a021737b95f36ff3b4612 Tue Nov 29 11:59:57 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rk3308: ddr: Update DDR bin to v2.07 20221129
Build from:
6ede97a868 dram_init: rk3308: Update to v2.07
Update features:
drivers: ram: rk3308: Change read DQS DLL delay to 45 if freq < 451MHz
drivers: ram: rk3308: Adjust print and delete useless code
drivers: ram: rk3308b-s: Fix config of phy pll
drivers: ram: rk3308: Fix ddrphy_dfi_clk4x_div_con of 294MHz
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ifba9759f35a99520833ba42f89021e1aee80744c
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| H A D | RK3308MINIALL_WO_FTL.ini | 5c96d2c0c5892ba3b98a021737b95f36ff3b4612 Tue Nov 29 11:59:57 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rk3308: ddr: Update DDR bin to v2.07 20221129
Build from:
6ede97a868 dram_init: rk3308: Update to v2.07
Update features:
drivers: ram: rk3308: Change read DQS DLL delay to 45 if freq < 451MHz
drivers: ram: rk3308: Adjust print and delete useless code
drivers: ram: rk3308b-s: Fix config of phy pll
drivers: ram: rk3308: Fix ddrphy_dfi_clk4x_div_con of 294MHz
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ifba9759f35a99520833ba42f89021e1aee80744c
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| H A D | RK3308MINIALL_UART4.ini | 5c96d2c0c5892ba3b98a021737b95f36ff3b4612 Tue Nov 29 11:59:57 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rk3308: ddr: Update DDR bin to v2.07 20221129
Build from:
6ede97a868 dram_init: rk3308: Update to v2.07
Update features:
drivers: ram: rk3308: Change read DQS DLL delay to 45 if freq < 451MHz
drivers: ram: rk3308: Adjust print and delete useless code
drivers: ram: rk3308b-s: Fix config of phy pll
drivers: ram: rk3308: Fix ddrphy_dfi_clk4x_div_con of 294MHz
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ifba9759f35a99520833ba42f89021e1aee80744c
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| H A D | RK3308MINIALL.ini | 5c96d2c0c5892ba3b98a021737b95f36ff3b4612 Tue Nov 29 11:59:57 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rk3308: ddr: Update DDR bin to v2.07 20221129
Build from:
6ede97a868 dram_init: rk3308: Update to v2.07
Update features:
drivers: ram: rk3308: Change read DQS DLL delay to 45 if freq < 451MHz
drivers: ram: rk3308: Adjust print and delete useless code
drivers: ram: rk3308b-s: Fix config of phy pll
drivers: ram: rk3308: Fix ddrphy_dfi_clk4x_div_con of 294MHz
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ifba9759f35a99520833ba42f89021e1aee80744c
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| /rkbin/doc/release/ |
| H A D | RK3308_EN.md | 5c96d2c0c5892ba3b98a021737b95f36ff3b4612 Tue Nov 29 11:59:57 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rk3308: ddr: Update DDR bin to v2.07 20221129
Build from:
6ede97a868 dram_init: rk3308: Update to v2.07
Update features:
drivers: ram: rk3308: Change read DQS DLL delay to 45 if freq < 451MHz
drivers: ram: rk3308: Adjust print and delete useless code
drivers: ram: rk3308b-s: Fix config of phy pll
drivers: ram: rk3308: Fix ddrphy_dfi_clk4x_div_con of 294MHz
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ifba9759f35a99520833ba42f89021e1aee80744c
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| H A D | RK3308_CN.md | 5c96d2c0c5892ba3b98a021737b95f36ff3b4612 Tue Nov 29 11:59:57 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rk3308: ddr: Update DDR bin to v2.07 20221129
Build from:
6ede97a868 dram_init: rk3308: Update to v2.07
Update features:
drivers: ram: rk3308: Change read DQS DLL delay to 45 if freq < 451MHz
drivers: ram: rk3308: Adjust print and delete useless code
drivers: ram: rk3308b-s: Fix config of phy pll
drivers: ram: rk3308: Fix ddrphy_dfi_clk4x_div_con of 294MHz
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ifba9759f35a99520833ba42f89021e1aee80744c
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