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| H A D | thread_a32.S | 52a109cdf90976413509a04ebcdcdff20d5d0152 Fri Nov 08 05:42:49 UTC 2019 Mark-PK Tsai <mark-pk.tsai@mediatek.com> core: arm32: disable interrupt in thread_excp_vect_workaround
thread_excp_vect_workaround isn't interrupt safe because it use
the tpidr as a temporary register to save value of r0.
That means if a fiq happened when optee is processing a syscall,
the syscall argument r0 will be changed to unexpected value.
Move `write_tpidrprw r0` out of `vector_prologue_spectre` and add
`cpsid aif` before it to fix this issue.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Reviewed-by: Alix Wu <alix.wu@mediatek.com>
Reviewed-by: YJ Chiang <yj.chiang@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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