Searched hist:"4 fe3a3f7bf3c6105fbf5a3c1ac5affbad720e1a8" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/riscv/kernel/ |
| H A D | asm-defines.c | 4fe3a3f7bf3c6105fbf5a3c1ac5affbad720e1a8 Mon Oct 23 09:32:28 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Refine thread trap handler
In order to support SMP, we made change on CSR SCRATCH from kernel stack
pointer to be kernel TP(thread_core_local). So that we can get TP from
SCRATCH easily in trap handler when the thread is in user mode. We also
save/restore CSR IE, kernel GP and SP so that we can handle task
migration to another hart.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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| H A D | thread_rv.S | 4fe3a3f7bf3c6105fbf5a3c1ac5affbad720e1a8 Mon Oct 23 09:32:28 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Refine thread trap handler
In order to support SMP, we made change on CSR SCRATCH from kernel stack
pointer to be kernel TP(thread_core_local). So that we can get TP from
SCRATCH easily in trap handler when the thread is in user mode. We also
save/restore CSR IE, kernel GP and SP so that we can handle task
migration to another hart.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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