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/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dclk.c4c90234586833c0bb4a5d9d3f69a69c8ab09e01f Sun Oct 04 22:18:45 UTC 2015 Vladimir Zapolskiy <vz@mleia.com> lpc32xx: fix calculation of HCLK PLL output clock

Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>