Searched hist:"1 e1dbad08c7644c91db2a235a1969b2f1c96be4f" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | socfpga_fcs.h | 1e1dbad08c7644c91db2a235a1969b2f1c96be4f Wed Mar 12 16:36:12 UTC 2025 Girisha Dengi <girisha.dengi@intel.com> fix(intel): update FCS AES method for GCM block modes
On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other platforms and other modes, it should
be in multiples of 32 bytes.
Change-Id: I0fa9adafb5d7fc4c794a4acb9339cf8259df0c78
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| H A D | socfpga_mailbox.h | 1e1dbad08c7644c91db2a235a1969b2f1c96be4f Wed Mar 12 16:36:12 UTC 2025 Girisha Dengi <girisha.dengi@intel.com> fix(intel): update FCS AES method for GCM block modes
On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other platforms and other modes, it should
be in multiples of 32 bytes.
Change-Id: I0fa9adafb5d7fc4c794a4acb9339cf8259df0c78
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/common/sip/ |
| H A D | socfpga_sip_fcs.c | 1e1dbad08c7644c91db2a235a1969b2f1c96be4f Wed Mar 12 16:36:12 UTC 2025 Girisha Dengi <girisha.dengi@intel.com> fix(intel): update FCS AES method for GCM block modes
On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other platforms and other modes, it should
be in multiples of 32 bytes.
Change-Id: I0fa9adafb5d7fc4c794a4acb9339cf8259df0c78
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|