Searched hist:"1552 df5d25944b2bddf42e96acbadca18b3c7c95" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/plat/imx/common/sci/svc/timer/ |
| H A D | timer_rpc_clnt.c | 1552df5d25944b2bddf42e96acbadca18b3c7c95 Tue Jan 15 02:22:06 UTC 2019 Anson Huang <Anson.Huang@nxp.com> Support for NXP's i.MX8 SoCs timer IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.
This patch adds timer IPC(inter-processor communication) support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
| H A D | sci_timer_rpc.h | 1552df5d25944b2bddf42e96acbadca18b3c7c95 Tue Jan 15 02:22:06 UTC 2019 Anson Huang <Anson.Huang@nxp.com> Support for NXP's i.MX8 SoCs timer IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.
This patch adds timer IPC(inter-processor communication) support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
| /rk3399_ARM-atf/plat/imx/common/include/sci/svc/timer/ |
| H A D | sci_timer_api.h | 1552df5d25944b2bddf42e96acbadca18b3c7c95 Tue Jan 15 02:22:06 UTC 2019 Anson Huang <Anson.Huang@nxp.com> Support for NXP's i.MX8 SoCs timer IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.
This patch adds timer IPC(inter-processor communication) support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
| /rk3399_ARM-atf/plat/imx/common/sci/ |
| H A D | sci_api.mk | 1552df5d25944b2bddf42e96acbadca18b3c7c95 Tue Jan 15 02:22:06 UTC 2019 Anson Huang <Anson.Huang@nxp.com> Support for NXP's i.MX8 SoCs timer IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.
This patch adds timer IPC(inter-processor communication) support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
| /rk3399_ARM-atf/plat/imx/common/include/sci/ |
| H A D | sci.h | 1552df5d25944b2bddf42e96acbadca18b3c7c95 Tue Jan 15 02:22:06 UTC 2019 Anson Huang <Anson.Huang@nxp.com> Support for NXP's i.MX8 SoCs timer IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.
This patch adds timer IPC(inter-processor communication) support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|