Home
last modified time | relevance | path

Searched hist:"0 c44e92445749f8b67f5730f29044babc6bd62cf" (Results 1 – 1 of 1) sorted by relevance

/optee_os/core/arch/riscv/kernel/
H A Dentry.S0c44e92445749f8b67f5730f29044babc6bd62cf Sun May 11 16:05:35 UTC 2025 Yu-Chien Peter Lin <peter.lin@sifive.com> core: riscv: enable MMU earlier for secondary cores

Enable MMU for secondary harts earlier to ensure
proper access to symbols in ASLR virtual addresses.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>