Searched +full:zynqmp +full:- +full:nand +full:- +full:controller (Results 1 – 8 of 8) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/mtd/arasan,nand-controller.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Arasan NAND Flash Controller with ONFI 3.1 support device tree bindings10 - $ref: "nand-controller.yaml"13 - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>18 - enum:19 - xlnx,zynqmp-nand-controller20 - const: arasan,nfc-v3p10[all …]
2 * dts file for Xilinx ZynqMP zc1751-xm016-dc28 * SPDX-License-Identifier: GPL-2.0+11 /dts-v1/;13 #include "zynqmp.dtsi"14 #include "zynqmp-clk.dtsi"17 model = "ZynqMP zc1751-xm016-dc2 RevA";18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";36 stdout-path = "serial0:115200n8";56 xlnx,include-sg; /* for testing purpose */59 xlnx,src-issue = <31>;[all …]
2 * dts file for Xilinx ZynqMP4 * (C) Copyright 2014 - 2015, Xilinx, Inc.8 * SPDX-License-Identifier: GPL-2.0+12 compatible = "xlnx,zynqmp";13 #address-cells = <2>;14 #size-cells = <2>;17 #address-cells = <1>;18 #size-cells = <0>;21 compatible = "arm,cortex-a53", "arm,armv8";23 enable-method = "psci";[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Arasan NAND Flash Controller Driver5 * Copyright (C) 2014 - 2020 Xilinx, Inc.17 #include <linux/dma-mapping.h>103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)111 * struct anfc_op - Defines how to execute an operation120 * @read: Data transfer direction from the controller point of view136 * struct anand - Defines the NAND chip related information137 * @node: Used to store NAND chips into a list138 * @chip: NAND chip information structure[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
4 * (C) Copyright 2000-20067 * SPDX-License-Identifier: GPL-2.0+31 #include <u-boot/md5.h>32 #include <u-boot/sha1.h>48 #include <u-boot/md5.h>57 #include <u-boot/crc.h>89 { IH_ARCH_RISCV, "riscv", "RISC-V", },90 { -1, "", "", },95 { IH_OS_OP_TEE, "op-tee", "OP-TEE" },96 { IH_OS_ARM_TRUSTED_FIRMWARE, "arm-trusted-firmware", "ARM Trusted Firmware" },[all …]
4 * (C) Copyright 2000-20057 * SPDX-License-Identifier: GPL-2.0+9 * NOTE: This header file defines an interface to U-Boot. Including11 * use of U-Boot, and does *not* fall under the heading of "derived44 #include <asm/u-boot.h>158 IH_OS_OP_TEE, /* OP-TEE */183 IH_ARCH_NIOS, /* Nios-32 */185 IH_ARCH_NIOS2, /* Nios-II */190 IH_ARCH_NDS32, /* ANDES Technology - NDS32 */196 IH_ARCH_RISCV, /* RISC-V */[all …]