Searched +full:tegra30 +full:- +full:mc (Results 1 – 25 of 25) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra30-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra30-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/soc/tegra-pmc.h>10 compatible = "nvidia,tegra30";11 interrupt-parent = <&lic>;12 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra114-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra114-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/soc/tegra-pmc.h>11 interrupt-parent = <&lic>;12 #address-cells = <1>;13 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra124-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra124-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/reset/tegra124-car.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>9 #include <dt-bindings/soc/tegra-pmc.h>13 interrupt-parent = <&lic>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra30 SoC Memory Controller10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>15 Tegra30 Memory Controller architecturally consists of the following parts:33 The Tegra30 Memory Controller handles memory requests from internal clients[all …]
1 # SPDX-License-Identifier: (GPL-2.0)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra30 SoC External Memory Controller10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>15 The EMC interfaces with the off-chip SDRAM to service the request stream16 sent from Memory Controller. The EMC also has various performance-affecting[all …]
1 #include <dt-bindings/clock/tegra30-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra30-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>10 compatible = "nvidia,tegra30";11 interrupt-parent = <&lic>;13 pcie-controller@00003000 {14 compatible = "nvidia,tegra30-pcie";19 reg-names = "pads", "afi", "cs";[all …]
1 #include <dt-bindings/clock/tegra114-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra114-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>11 interrupt-parent = <&lic>;14 compatible = "nvidia,tegra114-host1x", "simple-bus";20 reset-names = "host1x";22 #address-cells = <1>;23 #size-cells = <1>;[all …]
1 #include <dt-bindings/clock/tegra124-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra124-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/reset/tegra124-car.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>14 interrupt-parent = <&lic>;17 pcie-controller@01003000 {[all …]
1 #include <dt-bindings/clock/tegra210-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra210-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>10 interrupt-parent = <&lic>;11 #address-cells = <2>;12 #size-cells = <2>;14 pcie-controller@01003000 {[all …]
1 # SPDX-License-Identifier: GPL-2.02 tegra-mc-y := mc.o4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o[all …]
1 # SPDX-License-Identifier: GPL-2.0-only7 This driver supports the Memory Controller (MC) hardware found on21 bool "NVIDIA Tegra30 External Memory Controller driver"26 Tegra30 chips. The EMC controls the external DRAM on the board.
1 // SPDX-License-Identifier: GPL-2.0+3 * Tegra30 External Memory Controller driver5 * Based on downstream driver from NVIDIA and tegra124-emc.c6 * Copyright (C) 2011-2014 NVIDIA Corporation9 * Copyright (C) 2019 GRATE-DRIVER project29 #include "mc.h"328 struct tegra_mc *mc; member362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <linux/dma-mapping.h>20 #include "mc.h"24 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },27 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },30 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },33 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },36 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },39 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },45 static int tegra_mc_block_dma_common(struct tegra_mc *mc, in tegra_mc_block_dma_common() argument[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 #include <dt-bindings/memory/tegra30-mc.h>11 #include "mc.h"
4 - compatible : "nvidia,tegra30-smmu"5 - reg : Should contain 3 register banks(address and length) for each7 - interrupts : Should contain MC General interrupt.8 - nvidia,#asids : # of ASIDs9 - dma-window : IOVA start address and length.10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.14 compatible = "nvidia,tegra30-smmu";19 dma-window = <0 0x40000000>; /* IOVA start & length */
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra124-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra124-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>7 #include <dt-bindings/interrupt-controller/arm-gic.h>8 #include <dt-bindings/thermal/tegra124-soctherm.h>9 #include <dt-bindings/soc/tegra-pmc.h>13 interrupt-parent = <&lic>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra210-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra210-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/reset/tegra210-car.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/tegra124-soctherm.h>10 #include <dt-bindings/soc/tegra-pmc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra194-clock.h>3 #include <dt-bindings/gpio/tegra194-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>7 #include <dt-bindings/power/tegra194-powergate.h>8 #include <dt-bindings/reset/tegra194-reset.h>9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>10 #include <dt-bindings/memory/tegra194-mc.h>[all …]
4 - compatible : Must contain one of the following values:5 - "nvidia,tegra20-vde"6 - "nvidia,tegra30-vde"7 - "nvidia,tegra114-vde"8 - "nvidia,tegra124-vde"9 - "nvidia,tegra132-vde"10 - reg : Must contain an entry for each entry in reg-names.11 - reg-names : Must include the following entries:12 - sxe13 - bsev[all …]
2 * (C) Copyright 2010-20155 * SPDX-License-Identifier: GPL-2.0+14 #include <asm/arch/mc.h>15 #include <asm/arch-tegra/ap.h>16 #include <asm/arch-tegra/clock.h>17 #include <asm/arch-tegra/fuse.h>18 #include <asm/arch-tegra/pmc.h>19 #include <asm/arch-tegra/scu.h>20 #include <asm/arch-tegra/tegra.h>21 #include <asm/arch-tegra/warmboot.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <linux/clk-provider.h>16 #include <dt-bindings/clock/tegra30-car.h>19 #include "clk-id.h"593 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },594 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },595 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },599 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },600 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },602 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.16 #include <linux/dma-mapping.h>19 #include <soc/tegra/mc.h>33 struct tegra_mc *mc; member72 writel(value, smmu->regs + offset); in smmu_writel()77 return readl(smmu->regs + offset); in smmu_readl()87 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)119 /* per-SWGROUP SMMU_*_ASID register */134 #define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1))[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]