Searched +full:sun50i +full:- +full:a64 +full:- +full:dma (Results 1 – 20 of 20) sorted by relevance
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/sun50i-a64-ccu.h>7 #include <dt-bindings/clock/sun8i-de2.h>8 #include <dt-bindings/clock/sun8i-r-ccu.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/reset/sun50i-a64-ccu.h>11 #include <dt-bindings/reset/sun8i-de2.h>12 #include <dt-bindings/reset/sun8i-r-ccu.h>13 #include <dt-bindings/thermal/thermal.h>16 interrupt-parent = <&gic>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/clock/sun50i-h6-ccu.h>6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>7 #include <dt-bindings/clock/sun8i-de2.h>8 #include <dt-bindings/clock/sun8i-tcon-top.h>9 #include <dt-bindings/reset/sun50i-h6-ccu.h>10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>11 #include <dt-bindings/reset/sun8i-de2.h>12 #include <dt-bindings/thermal/thermal.h>[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/dma/allwinner,sun50i-a64-dma.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Allwinner A64 DMA Controller Device Tree Bindings10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>14 - $ref: "dma-controller.yaml#"17 "#dma-cells":23 - const: allwinner,sun50i-a64-dma[all …]
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>14 "#sound-dai-cells":19 - const: allwinner,sun4i-a10-i2s20 - const: allwinner,sun6i-a31-i2s21 - const: allwinner,sun8i-a83t-i2s[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-spdif.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chen-Yu Tsai <wens@csie.org>11 - Liam Girdwood <lgirdwood@gmail.com>12 - Mark Brown <broonie@kernel.org>13 - Maxime Ripard <mripard@kernel.org>16 "#sound-dai-cells":21 - const: allwinner,sun4i-a10-spdif[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Alexandre Torgue <alexandre.torgue@st.com>11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>12 - Jose Abreu <joabreu@synopsys.com>23 - snps,dwmac24 - snps,dwmac-3.50a25 - snps,dwmac-3.61026 - snps,dwmac-3.70a[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>15 will use to perform DMA. It also has a register interface that19 Each device having to perform their DMA through the MBUS must have20 the interconnects and interconnect-names properties set to the MBUS21 controller and with "dma-mem" as the interconnect name.[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/media/allwinner,sun8i-h3-deinterlace.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Jernej Skrabec <jernej.skrabec@siol.net>11 - Chen-Yu Tsai <wens@csie.org>12 - Maxime Ripard <mripard@kernel.org>14 description: |-21 - const: allwinner,sun8i-h3-deinterlace22 - items:[all …]
2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>5 * This file is dual-licensed: you can use it either under the terms44 #include <dt-bindings/interrupt-controller/arm-gic.h>45 #include <dt-bindings/clock/sun8i-de2.h>46 #include <dt-bindings/clock/sun8i-r40-ccu.h>47 #include <dt-bindings/clock/sun8i-tcon-top.h>48 #include <dt-bindings/reset/sun8i-r40-ccu.h>49 #include <dt-bindings/reset/sun8i-de2.h>50 #include <dt-bindings/thermal/thermal.h>53 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)10 #include <linux/dma-mapping.h>30 #define MODULE_NAME "sun6i-csi"60 if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL in sun6i_csi_is_format_supported()61 || sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656) in sun6i_csi_is_format_supported()62 && sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) { in sun6i_csi_is_format_supported()79 dev_dbg(sdev->dev, "Unsupported mbus code: 0x%x\n", in sun6i_csi_is_format_supported()85 dev_dbg(sdev->dev, "Unsupported pixformat: 0x%x\n", in sun6i_csi_is_format_supported()142 dev_dbg(sdev->dev, "Unsupported mbus code: 0x%x\n", in sun6i_csi_is_format_supported()[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>18 "#clock-cells":23 - const: allwinner,sun4i-a10-tcon24 - const: allwinner,sun5i-a13-tcon25 - const: allwinner,sun6i-a31-tcon[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later11 #include <linux/dma-mapping.h>248 return -EINVAL; in sun8i_mixer_drm_format_to_hw()255 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, in sun8i_mixer_commit()266 planes = devm_kcalloc(drm->dev, in sun8i_layers_init()267 mixer->cfg->vi_num + mixer->cfg->ui_num + 1, in sun8i_layers_init()270 return ERR_PTR(-ENOMEM); in sun8i_layers_init()272 for (i = 0; i < mixer->cfg->vi_num; i++) { in sun8i_layers_init()277 dev_err(drm->dev, in sun8i_layers_init()282 planes[i] = &layer->plane; in sun8i_layers_init()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>13 #include <linux/clk/sunxi-ng.h>16 #include <linux/dma-mapping.h>27 #include <linux/mmc/slot-gpio.h>69 /* New registers introduced in A64 */[all …]
5 * SPDX-License-Identifier: GPL-2.0+7 * Ethernet driver for H3/A64/A83T based SoC's10 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!25 #include <asm-generic/gpio.h>38 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */74 /* H3/A64 EMAC Register's offset */148 struct udevice *dev = bus->priv; in sun8i_mdio_read()166 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); in sun8i_mdio_read()170 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY)) in sun8i_mdio_read()171 return readl(priv->mac_reg + EMAC_MII_DATA); in sun8i_mdio_read()[all …]
20 stand-alone devices. Useful in particular for systems that support21 DM_ETH and have a stand-alone MDIO hardware block shared by multiple23 This is currently implemented in net/mdio-uclass.c61 bool "Altera Triple-Speed Ethernet MAC support"65 This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.66 Please find details on the "Triple-Speed Ethernet MegaCore Function74 to MAC and DMA management for multiple Broadcom SoCs such as143 U-Boot.161 in U-Boot to the RAW AF_PACKET API in Linux. This allows real219 Enable the support of the Reduced Gigabit Media-Independent[all …]
1 // SPDX-License-Identifier: GPL-2.03 * sun8i-ce-core.c - hardware cryptographic offloader for4 * Allwinner H3/A64/H5/H2+/H6/R40 SoC6 * Copyright (C) 2015-2019 Corentin Labbe <clabbe.montjoie@gmail.com>15 #include <linux/dma-mapping.h>28 #include "sun8i-ce.h"31 * mod clock is lower on H3 than other SoC due to some DMA timeout occurring128 * This is a simple round-robin way of getting the next channel133 return atomic_inc_return(&ce->flow) % (MAXFLOW - 1); in sun8i_ce_get_engine_number()140 struct ce_task *cet = ce->chanlist[flow].tl; in sun8i_ce_run_task()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 #include <linux/clk-provider.h>24 #include "ccu-sun50i-a64.h"35 .hw.init = CLK_HW_INIT("pll-cpux",47 * With sigma-delta modulation for fractional-N on the audio PLL,61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd7 * Maxime Ripard <maxime.ripard@free-electrons.com>23 #include "virt-dma.h"120 * It's named "DMA MCLK interface circuit auto gating bit" in the122 * should be set up when initializing the DMA controller.153 * This field is not used by the DMA controller, but will be207 return &chan->dev->device; in chan2dev()228 dev_dbg(sdev->slave.dev, "Common register:\n" in sun6i_dma_dump_com_regs()234 DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), in sun6i_dma_dump_com_regs()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer11 #include <linux/mdio-mux.h>26 /* General notes on dwmac-sun8i:31 /* struct emac_variant - Describe dwmac-sun8i hardware variant59 /* struct sunxi_priv_data - hold all sunxi private data68 * @mux_handle: Internal pointer used by mdio-mux lib147 * co-packaged AC200 chip instead.254 /* H3/A64 specific bits */267 /* sun8i_dwmac_dma_reset() - reset the EMAC[all …]
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