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Searched +full:sgmii +full:- +full:ref +full:- +full:clock +full:- +full:output +full:- +full:enable (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 ti,min-output-impedance:
37 MAC Interface Impedance control to set the programmable output impedance
40 ti,max-output-impedance:
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/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.c4 * SPDX-License-Identifier: GPL-2.0
25 * serdes_seq_db - holds all serdes sequences, their size and the
31 #define ENDED_OK "High speed PHY - Ended Successfully\n"
64 /* Selector mapping for A380-A0 and A390-Z1 */
145 * SATA and SGMII
159 /* Rx clk and Tx clk select non-inverted mode */
178 /* Rx clk and Tx clk select non-inverted mode */
186 /* SATA and SGMII - power up seq */
189 * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
199 /* Ref clock source select */
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/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <dt-bindings/net/ti-dp83867.h>
184 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
191 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
196 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
197 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
200 return -EINVAL; in dp83867_set_wol()
214 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
216 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
218 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
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/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
36 /*-----------------------------------------------------------*/
114 for (; timeout > 0; timeout--) { in comphy_poll_reg()
142 * 1. Enable max PLL. in comphy_pcie_power_up()
165 * 5. Enable idle sync in comphy_pcie_power_up()
171 * 6. Enable the output of 100M/125M/500M clock in comphy_pcie_power_up()
177 * 7. Enable TX in comphy_pcie_power_up()
256 * 1. Select 40-bit data width width in comphy_sata_power_up()
262 * 2. Select reference clock and PHY mode (SATA) in comphy_sata_power_up()
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H A Dcomphy_cp110.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
32 * For CP-110 we have 2 Selector registers "PHY Selectors",
79 } while (data != val && --usec_timout > 0); in polling_with_timeout()
101 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
103 * U-Boot to mainline version. in comphy_pcie_power_up()
105 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()
106 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up()
108 debug("PCIe clock = %x\n", pcie_clk); in comphy_pcie_power_up()
112 /* enable PCIe by4 and by2 */ in comphy_pcie_power_up()
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/OK3568_Linux_fs/kernel/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
365 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
367 writew(val, ctx->base + offset); in cdns_regmap_write()
375 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
377 *val = readw(ctx->base + offset); in cdns_regmap_read()
387 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
398 *val = readl(ctx->base + offset); in cdns_regmap_dptx_read()
497 * Structure used to store values of PHY registers for voltage-related
498 * coefficients, for particular voltage swing and pre-emphasis level. Values
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/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c4 * SPDX-License-Identifier: GPL-2.0
18 #define ENDED_OK "High speed PHY - Ended Successfully\n"
193 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val]; in board_serdes_cfg_get()
214 return (info->line0_7 >> (line_num << 2)) & 0xF; in get_line_cfg()
216 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; in get_line_cfg()
236 * non-established PCIe links (link down). Especially under certain
238 * To enable a board-specific detection pulse width this weak
240 * overwritten if needed by a board-specific version. If the board
241 * code does not provide a non-weak version of this variable, the
287 DEBUG_INIT_S("High speed PHY - Version: "); in serdes_phy_config()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
42 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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