| /OK3568_Linux_fs/kernel/arch/arm/mach-lpc32xx/ |
| H A D | suspend.S | 2 * arch/arm/mach-lpc32xx/suspend.S
41 stmfd r0!, {r3 - r7, sp, lr}
65 @ Setup self-refresh with support for manual exit of
66 @ self-refresh mode
72 @ Wait for self-refresh acknowledge, clocks to the DRAM device
73 @ will automatically stop on start of self-refresh
78 bne 3b @ Branch until self-refresh mode starts
80 @ Enter direct-run mode from run mode
115 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
116 @ update yet. DRAM is still in self-refresh
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| H A D | pm.c | 2 * arch/arm/mach-lpc32xx/pm.c
17 * direct-run, and halt modes. When switching between halt and run modes,
18 * the CPU transistions through direct-run mode. For Linux, direct-run
27 * Direct-run mode:
38 * wake the system up back into direct-run mode.
40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transition to direct-run mode will stop all DDR accesses (no clocks).
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/ |
| H A D | drm_self_refresh_helper.c | 1 // SPDX-License-Identifier: MIT
27 * framework to implement panel self refresh (SR) support. Drivers are
31 * &drm_connector_state.self_refresh_aware to true at runtime if it is SR-aware
32 * (meaning it knows how to initiate self refresh on the panel).
38 * that tells you to disable/enable SR on the panel instead of power-cycling it.
72 struct drm_crtc *crtc = sr_data->crtc; in drm_self_refresh_helper_entry_work()
73 struct drm_device *dev = crtc->dev; in drm_self_refresh_helper_entry_work()
85 ret = -ENOMEM; in drm_self_refresh_helper_entry_work()
90 state->acquire_ctx = &ctx; in drm_self_refresh_helper_entry_work()
98 if (!crtc_state->enable) in drm_self_refresh_helper_entry_work()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dram/ |
| H A D | rk3399_dram_timing.txt | 4 - compatible : Should be "rockchip,ddr-timing"
6 - ddr3_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h.
7 It select DDR3 cl-trp-trcd type, default value "DDR3_DEFAULT".it must selected
11 - pd_idle : Defines the power-down mode auto entry controller clocks.
14 power-down low power state.
16 - sr_idle : Defines the Self-Refresh or Self-Refresh with Memory Clock Gating
19 before the controller will automatically issue an entry into the Self-Refresh
20 or Self-Refresh with Memory Clock Gating low power state.
22 - sr_mc_gate_idle : Defined the Self-Refresh with Memory and Controller Clock Gating
25 the controller will automatically issue an entry into the Self-Refresh with
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| /OK3568_Linux_fs/u-boot/tools/dtoc/ |
| H A D | fdt.py | 6 # SPDX-License-Identifier: GPL-2.0+
17 # contains the base classes and defines the high-level API. You can use
40 def __init__(self, node, offset, name, bytes): argument
41 self._node = node
42 self._offset = offset
43 self.name = name
44 self.value = None
45 self.bytes = str(bytes)
47 self.type = TYPE_BOOL
48 self.value = True
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| /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
18 -logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-su…
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| /OK3568_Linux_fs/kernel/arch/arm/mach-socfpga/ |
| H A D | self-refresh.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
32 .arch armv7-a
44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
125 .word . - socfpga_sdram_self_refresh
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| /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/ |
| H A D | sleep.S | 2 * Low-level PXA250/210 sleep/wakeUp support
18 #include <mach/pxa2xx-regs.h>
27 * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
61 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
106 @ We keep the change-down close to the actual suspend on SDRAM
107 @ as possible to eliminate messing about with the refresh clock
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| /OK3568_Linux_fs/kernel/drivers/cpuidle/ |
| H A D | cpuidle-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Xilinx
7 * based on arch/arm/mach-at91/cpuidle.c
9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
10 * to implement two idle states -
11 * #1 wait-for-interrupt
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
61 .name = "cpuidle-zynq",
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| /OK3568_Linux_fs/kernel/arch/sh/boards/mach-kfr2r09/ |
| H A D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * KFR2R09 sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/devfreq/ |
| H A D | rk3399_dmc.txt | 4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
21 - rockchip,pmu: Phandle to the syscon managing the "PMU general register
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| /OK3568_Linux_fs/kernel/arch/sh/boards/mach-migor/ |
| H A D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Migo-R sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
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| /OK3568_Linux_fs/kernel/arch/sh/boards/mach-ap325rxa/ |
| H A D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * AP325RXA sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
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| /OK3568_Linux_fs/kernel/arch/arm/mach-at91/ |
| H A D | pm_suspend.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
77 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
81 stmfd sp!, {r4 - r12, lr}
111 /* Active the self-refresh mode */
135 /* Exit the self-refresh mode */
140 ldmfd sp!, {r4 - r12, pc}
274 /* Switch the main clock source to 12-MHz RC oscillator */
511 * - MAINCK if using ULP0 fast variant
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| /OK3568_Linux_fs/yocto/poky/meta/lib/oe/ |
| H A D | patch.py | 2 # SPDX-License-Identifier: GPL-2.0-only
10 def __init__(self, path): argument
11 self.path = path
13 def __str__(self): argument
14 return "Error: %s not found." % self.path
17 def __init__(self, command, exitstatus, output): argument
18 self.command = command
19 self.status = exitstatus
20 self.output = output
22 def __str__(self): argument
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| /OK3568_Linux_fs/yocto/poky/bitbake/lib/toaster/tests/browser/ |
| H A D | test_layerdetails_page.py | 5 # SPDX-License-Identifier: GPL-2.0-only
7 # Copyright (C) 2013-2016 Intel Corporation
24 def __init__(self, *args, **kwargs): argument
25 super(TestLayerDetailsPage, self).__init__(*args, **kwargs)
27 self.initial_values = None
28 self.url = None
29 self.imported_layer_version = None
31 def setUp(self): argument
38 self.project = Project.objects.create(name='foo', release=release)
40 name = "meta-imported"
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| /OK3568_Linux_fs/kernel/arch/sh/kernel/cpu/shmobile/ |
| H A D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0
28 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
29 * Standby Self-Refresh mode is above plus stopped clocks
37 * U-standby mode is unsupported since it needs bootloader hacks
62 /* Let assembly snippet in on-chip memory handle the rest */ in sh_mobile_call_standby()
88 sdp->addr.stbcr = 0xa4150020; /* STBCR */ in sh_mobile_register_self_refresh()
89 sdp->addr.bar = 0xa4150040; /* BAR */ in sh_mobile_register_self_refresh()
90 sdp->addr.pteh = 0xff000000; /* PTEH */ in sh_mobile_register_self_refresh()
91 sdp->addr.ptel = 0xff000004; /* PTEL */ in sh_mobile_register_self_refresh()
92 sdp->addr.ttb = 0xff000008; /* TTB */ in sh_mobile_register_self_refresh()
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| /OK3568_Linux_fs/kernel/arch/sh/boards/mach-ecovec24/ |
| H A D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Ecovec24 sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
41 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /OK3568_Linux_fs/kernel/arch/sh/boards/mach-se/7724/ |
| H A D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * MS7724SE sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
72 /* DBSC: re-initialize and put in auto-refresh */
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| /OK3568_Linux_fs/kernel/include/soc/at91/ |
| H A D | at91sam9_sdramc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
57 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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| H A D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
22 #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
81 #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
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| /OK3568_Linux_fs/kernel/arch/arm/mach-imx/ |
| H A D | suspend-imx53.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
60 /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */
66 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */
115 /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */
121 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */
134 .word . - imx53_suspend
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91sam9_sdramc.h | 2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
11 * SPDX-License-Identifier: GPL-2.0+
56 #define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
57 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
89 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
93 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
98 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
99 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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| /OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_dfs.c | 4 * SPDX-License-Identifier: GPL-2.0
73 /* Poll - Wait for Refresh operation completion */ in wait_refresh_op_complete()
83 * Args: target_freq - target frequency
85 * Returns: freq_par - the ratio parameter
96 /* Find the ratio between PLL frequency and ddr-clk */ in ddr3_get_freq_parameter()
109 * Args: freq - target frequency
111 * Returns: MV_OK - success, MV_FAIL - fail
120 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
123 /* target frequency - 100MHz */ in ddr3_dfs_high_2_low()
132 /* Configure - DRAM DLL final state after DFS is complete - Enable */ in ddr3_dfs_high_2_low()
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| /OK3568_Linux_fs/buildroot/package/python-setuptools/ |
| H A D | 0001-add-executable.patch | 2 From: =?UTF-8?q?J=C3=B6rg=20Krause?= <joerg.krause@embedded.rocks>
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 Add a new --executable option to distribute so that we can
12 [Thomas: refresh for setuptools 5.8.]
13 [Jörg: refresh for setuptools 18.7.1]
15 Signed-off-by: Gustavo Zacarias <gustavo@zacarias.com.ar>
16 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
17 Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
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