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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
16 const: intel,lgm-pcie
18 - compatible
23 - const: intel,lgm-pcie
24 - const: snps,dw-pcie
29 "#address-cells":
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock DT bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
18 - enum:
19 - ingenic,jz4740-rtc
20 - ingenic,jz4760-rtc
21 - items:
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/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_arria10.c2 * Copyright (C) 2016-2017 Intel Corporation
4 * SPDX-License-Identifier: GPL-2.0
31 void socfpga_reset_uart(int assert) in socfpga_reset_uart() argument
35 com_port = uart_com_port(gd->fdt_blob); in socfpga_reset_uart()
38 socfpga_per_reset(SOCFPGA_RESET(UART1), assert); in socfpga_reset_uart()
40 socfpga_per_reset(SOCFPGA_RESET(UART0), assert); in socfpga_reset_uart()
128 /* Disable the watchdog (toggle reset to watchdog) */
131 /* assert reset for watchdog */ in socfpga_watchdog_disable()
132 setbits_le32(&reset_manager_base->per1modrst, in socfpga_watchdog_disable()
136 /* Release NOC ddr scheduler from reset */
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/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dmesh.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
12 * Add delay after initial bus reset
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
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/OK3568_Linux_fs/u-boot/arch/x86/cpu/quark/
H A Dquark.c4 * SPDX-License-Identifier: GPL-2.0+
46 mask = ~(CONFIG_SYS_MONITOR_LEN - 1); in quark_setup_mtrr()
54 mask = ~(ESRAM_SIZE - 1); in quark_setup_mtrr()
70 /* GPIO - D31:F0:R44h */ in quark_setup_bars()
74 /* ACPI PM1 Block - D31:F0:R48h */ in quark_setup_bars()
78 /* GPE0 - D31:F0:R4Ch */ in quark_setup_bars()
82 /* WDT - D31:F0:R84h */ in quark_setup_bars()
86 /* RCBA - D31:F0:RF0h */ in quark_setup_bars()
90 /* ACPI P Block - Msg Port 04:R70h */ in quark_setup_bars()
94 /* SPI DMA - Msg Port 04:R7Ah */ in quark_setup_bars()
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c3 * Author: Chen-Yu Tsai <wens@csie.org>
6 * which was based on code by Carl van Schaik <carl@ok-labs.com>.
8 * SPDX-License-Identifier: GPL-2.0
33 * The power clamps are located in the unused space after the per-core
34 * reset controls for core 3. The secondary core entry address register
62 static void __secure __mdelay(u32 ms) in __mdelay() argument
64 u32 reg = ONE_MS * ms; in __mdelay()
134 writel((u32)entry, &cpucfg->priv0); in sunxi_set_entry_address()
145 sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, in sunxi_cpu_set_power()
164 sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, in sunxi_cpu_set_power()
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/OK3568_Linux_fs/u-boot/doc/
H A DREADME.i2c4 While I2C supports multi-master buses this is difficult to get right.
6 Clock-stretching and the arbitrary time that an I2C transaction can take
8 When one or more masters can be reset independently part-way through a
11 U-Boot provides a scheme based on two 'claim' GPIOs, one driven by the
18 Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO,
23 i2c-arb-gpio-challenge for the implementation.
28 - AP_CLAIM: output from AP, signalling to the EC that the AP wants the bus
29 - EC_CLAIM: output from EC, signalling to the AP that the EC wants the bus
31 The basic algorithm is to assert your line when you want the bus, then make
50 To release the bus, just de-assert the claim line.
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/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
66 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
76 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); in jz4740_rtc_wait_write_ready()
78 return timeout ? 0 : -EIO; in jz4740_rtc_wait_write_ready()
90 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
93 ctrl = readl(rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
94 } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout); in jz4780_rtc_enable_write()
96 return timeout ? 0 : -EIO; in jz4780_rtc_enable_write()
104 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/
H A Dpcie_core.c23 * <<Broadcom-WL-IPTag/Dual:>>
60 * WAR for CRWLPCIEGEN2-163, needed for all the chips at this point.
62 * to the PCIe configuration registers. When chip backplane reset hits, e.g. on driver unload, the
63 * pcie snoop out will reset to default values and may get out of sync with pcie config registers.
83 * JIRA : SWWLAN-283651, 4397A0 WAR : During insmod avoid existing in pcie_watchdog_reset()
86 if (BCM4397_CHIP(sih->chip)) { in pcie_watchdog_reset()
90 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
91 if (CCREV(sih->ccrev) < 65) { in pcie_watchdog_reset()
97 if (CCREV(sih->ccrev) < 67) { in pcie_watchdog_reset()
98 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
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/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/
H A Dpcie_core.c23 * <<Broadcom-WL-IPTag/Dual:>>
60 * WAR for CRWLPCIEGEN2-163, needed for all the chips at this point.
62 * to the PCIe configuration registers. When chip backplane reset hits, e.g. on driver unload, the
63 * pcie snoop out will reset to default values and may get out of sync with pcie config registers.
83 * JIRA : SWWLAN-283651, 4397A0 WAR : During insmod avoid existing in pcie_watchdog_reset()
86 if (BCM4397_CHIP(sih->chip)) { in pcie_watchdog_reset()
90 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
91 if (CCREV(sih->ccrev) < 65) { in pcie_watchdog_reset()
97 if (CCREV(sih->ccrev) < 67) { in pcie_watchdog_reset()
98 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
20 When not specified, the hardware default of 1300ms
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/OK3568_Linux_fs/u-boot/board/Synology/ds109/
H A Dopenocd.cfg7 ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
8 ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
12 # length of reset signal: [ms]
15 # don't talk to JTAG after reset for: [ms]
24 # We need to assert DBGRQ while holding nSRST down.
29 # re-examine the target again here when nSRST is asserted which
36 #reset run
111 # load u-Boot into RAM and execute it
113 load_image u-boot.bin 0x00600000 bin
/OK3568_Linux_fs/kernel/drivers/net/wireless/intersil/orinoco/
H A Dorinoco_pci.c4 * (i.e. these are not PCMCIA cards in a PCMCIA-to-PCI bridge).
14 * Some of this code is "inspired" by linux-wlan-ng-0.1.10, but nothing
15 * has been copied from it. linux-wlan-ng-0.1.10 is originally :
20 * (C) Copyright David Gibson, IBM Corp. 2002-2003.
59 /* Bitmask to reset the card */
62 /* Magic timeouts for doing the reset.
63 * Those times are straight from wlan-ng, and it is claimed that they
65 #define HERMES_PCI_COR_ONT (250) /* ms */
66 #define HERMES_PCI_COR_OFFT (500) /* ms */
67 #define HERMES_PCI_COR_BUSYT (500) /* ms */
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/OK3568_Linux_fs/u-boot/drivers/pci/
H A Dpcie_imx.c2 * Freescale i.MX6 PCI Express Root-Complex driver
7 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
8 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
10 * SPDX-License-Identifier: GPL-2.0
43 /* PCIe Port Logic registers (memory-mapped) */
64 /* PHY registers (not memory-mapped) */
116 return -ETIMEDOUT; in pcie_phy_poll_ack()
144 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
154 /* assert Read signal */ in pcie_phy_read()
201 /* wait for ack de-assertion */ in pcie_phy_write()
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/OK3568_Linux_fs/kernel/drivers/macintosh/
H A Dmediabay.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
33 #define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
76 * Wait that number of ms between each step in normal polling mode
81 * Consider the media-bay ID value stable if it is the same for
86 /* Wait after powering up the media bay this delay in ms
92 * Hold the media-bay reset signal true for this many ticks
98 * Wait this long after the reset signal is released and before doing
99 * further operations. After this delay, the IDE reset signal is released
105 * Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
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/OK3568_Linux_fs/kernel/drivers/phy/ralink/
H A Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/reset.h>
63 writel(val, phy->base + reg); in u2_phy_w32()
68 return readl(phy->base + reg); in u2_phy_r32()
97 regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, in ralink_usb_phy_power_on()
98 phy->clk, phy->clk); in ralink_usb_phy_power_on()
101 regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, in ralink_usb_phy_power_on()
105 /* deassert the reset lines */ in ralink_usb_phy_power_on()
106 reset_control_deassert(phy->rsthost); in ralink_usb_phy_power_on()
107 reset_control_deassert(phy->rstdev); in ralink_usb_phy_power_on()
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
14 pp1250_s3: pp1250-s3 {
15 compatible = "regulator-fixed";
16 regulator-name = "pp1250_s3";
19 regulator-always-on;
20 regulator-boot-on;
21 regulator-min-microvolt = <1250000>;
22 regulator-max-microvolt = <1250000>;
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/OK3568_Linux_fs/kernel/drivers/pps/clients/
H A Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
19 #include <linux/pps-gpio.h>
34 struct timer_list echo_timer; /* timer to reset echo active state */
56 rising_edge = gpiod_get_value(info->gpio_pin); in pps_gpio_irq_handler()
57 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
58 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
59 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
60 else if (info->capture_clear && in pps_gpio_irq_handler()
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/OK3568_Linux_fs/kernel/drivers/watchdog/
H A Dpnx4008_wdt.c1 // SPDX-License-Identifier: GPL-2.0
12 * 2005-2006 (c) MontaVista Software, Inc.
34 /* WatchDog Timer - Chapter 23 Page 207 */
87 /* stop counter, initiate counter reset */ in pnx4008_wdt_start()
89 /*wait for reset to complete. 100% guarantee event */ in pnx4008_wdt_start()
92 /* internal and external reset, stop after that */ in pnx4008_wdt_start()
98 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ in pnx4008_wdt_start()
100 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start()
121 wdd->timeout = new_timeout; in pnx4008_wdt_set_timeout()
133 * - For details, see the 'reboot' syscall in kernel/reboot.c in pnx4008_restart_handler()
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/OK3568_Linux_fs/kernel/include/linux/
H A Drmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011-2016 Synaptics Incorporated
21 * struct rmi_2d_axis_alignment - target axis alignment
22 * @swap_axes: set to TRUE if desired to swap x- and y-axis
23 * @flip_x: set to TRUE if desired to flip direction on x-axis
24 * @flip_y: set to TRUE if desired to flip direction on y-axis
25 * @clip_x_low - reported X coordinates below this setting will be clipped to
27 * @clip_x_high - reported X coordinates above this setting will be clipped to
29 * @clip_y_low - reported Y coordinates below this setting will be clipped to
31 * @clip_y_high - reported Y coordinates above this setting will be clipped to
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/OK3568_Linux_fs/u-boot/cmd/
H A Dtpm_test.c4 * SPDX-License-Identifier: GPL-2.0+
183 assert(disable == 1 && deactivated == 1); in test_fast_enable()
189 assert(disable == 0 && deactivated == 0); in test_fast_enable()
216 assert(result == TPM_AREA_LOCKED); in test_global_lock()
218 assert(x == 0); in test_global_lock()
223 assert(x == 2); in test_global_lock()
229 assert(result == TPM_BAD_PRESENCE); in test_global_lock()
231 assert(x == 2); in test_global_lock()
281 * Checks if initialisation has completed by trying to read-lock a in test_readonly()
328 assert(!tpm_is_owned()); in test_redefine_unowned()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/
H A Dsiutils.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Misc utility routines for accessing chip-specific features
4 * of the SiliconBackplane-based Broadcom chips.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: siutils.c 668442 2016-11-03 08:42:43Z $
139 * devid - pci device id (used to determine chip#)
140 * osh - opaque OS handle
141 * regs - virtual address of initial core registers
142 * bustype - pci/pcmcia/sb/sdio/etc
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H A Dlinux_osl.c1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 1999-2017, Broadcom Corporation
26 * <<Broadcom-WL-IPTag/Open:>>
28 * $Id: linux_osl.c 680580 2017-01-20 11:49:58Z $
55 #include <asm-generic/pci-dma-compat.h>
71 #include <linux/dma-mapping.h>
107 #define DHD_SKB_1PAGE_BUFSIZE ((PAGE_SIZE*1)-DHD_SKB_HDRSIZE)
108 #define DHD_SKB_2PAGE_BUFSIZE ((PAGE_SIZE*2)-DHD_SKB_HDRSIZE)
109 #define DHD_SKB_4PAGE_BUFSIZE ((PAGE_SIZE*4)-DHD_SKB_HDRSIZE)
249 ASSERT(OSL_PKTTAG_SZ == 32); \
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb/
H A Dpm3393.c7 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
96 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
102 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
106 /* Port reset. */
124 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
147 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
153 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_enable()
154 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
156 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
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/OK3568_Linux_fs/kernel/drivers/pci/controller/dwc/
H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
31 #include <linux/reset.h>
35 #include "pcie-designware.h"
43 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
96 /* PCIe Port Logic registers (memory-mapped) */
109 /* PHY registers (not memory-mapped) */
146 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_poll_ack()
162 return -ETIMEDOUT; in pcie_phy_poll_ack()
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