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/OK3568_Linux_fs/u-boot/include/linux/
H A Dmdio.h3 * Copyright 2006-2009 Solarflare Communications Inc.
20 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
23 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
38 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
39 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
40 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
45 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
47 /* Media-dependent registers. */
48 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
49 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
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/OK3568_Linux_fs/kernel/include/uapi/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
51 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
57 /* Media-dependent registers. */
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
49 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
53 /* Media-dependent registers. */
54 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
49 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
53 /* Media-dependent registers. */
54 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
12 * genphy_c45_setup_forced - configures a forced speed
20 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
21 return -EINVAL; in genphy_c45_pma_setup_forced()
33 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 in genphy_c45_pma_setup_forced()
34 * in 802.3-2012 and 802.3-2015. in genphy_c45_pma_setup_forced()
38 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
48 /* Assume 1000base-T */ in genphy_c45_pma_setup_forced()
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H A Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY Device Tree Bindings
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
23 reg-names:
25 - const: phy-pma
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H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USBDP Combo PHY with Samsung IP block
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
23 - description: phy ref clock.
24 - description: phy pcs immortal clock.
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/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dxilinx_phy.c2 * Xilinx PCS/PMA Core phy driver
4 * Copyright (C) 2015 - 2016 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <phy.h>
25 /* Known PHY IDs */
49 if (AUTONEG_ENABLE == phydev->autoneg) { in xilinxphy_startup()
54 phydev->duplex = DUPLEX_FULL; in xilinxphy_startup()
56 phydev->duplex = DUPLEX_HALF; in xilinxphy_startup()
60 phydev->speed = SPEED_1000; in xilinxphy_startup()
64 phydev->speed = SPEED_100; in xilinxphy_startup()
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H A Dgeneric_10g.c2 * Generic PHY Management code
4 * SPDX-License-Identifier: GPL-2.0+
9 * Based loosely off of Linux's PHY Lib
15 #include <phy.h>
25 u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK; in gen10g_startup()
27 phydev->link = 1; in gen10g_startup()
30 phydev->speed = SPEED_10000; in gen10g_startup()
31 phydev->duplex = DUPLEX_FULL; in gen10g_startup()
34 * Go through all the link-reporting devices, and make sure in gen10g_startup()
46 phydev->link = 0; in gen10g_startup()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/sfc/falcon/
H A Dqt202x_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2012 Solarflare Communications Inc.
15 #include "phy.h"
27 /* Quake-specific MDIO registers */
85 ((1 << PCS_FW_HEARTB_WIDTH) - 1)); in qt2025c_wait_heartbeat()
92 * PHY's on-board EEPROM so it cannot load firmware */ in qt2025c_wait_heartbeat()
93 netif_err(efx, hw, efx->net_dev, in qt2025c_wait_heartbeat()
97 return -ETIMEDOUT; in qt2025c_wait_heartbeat()
116 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= in qt2025c_wait_fw_status_good()
120 return -ETIMEDOUT; in qt2025c_wait_fw_status_good()
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H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
16 #include "phy.h"
30 * Compile-time config
35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
69 /* Lane power-down */
108 /* Lane power-down */
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/OK3568_Linux_fs/kernel/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
9 #include <dt-bindings/phy/phy.h>
20 #include <linux/phy/phy.h>
56 * register offsets from DPTX PHY register block base (i.e MHDP
76 * register offsets from SD0801 PHY register block base (i.e MHDP
161 /* PMA TX Lane registers */
180 /* PMA RX Lane registers */
208 /* PHY PCS common registers */
214 /* PHY PMA common registers */
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/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-snps-pcie3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy-snps-pcie3.h>
49 struct phy *phy; member
59 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
61 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
66 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
69 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
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H A Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
11 * PHY to switch mode between USB3 and USB3+DP, without disconnecting the USB
27 * If EXTCON_USB_HOST state is true, it is DP + USB2 mode, since the USB2 phy
28 * is a separate phy, so this case is still DP only mode.
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
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/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-snps-pcie3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
12 #include <generic-phy.h>
17 #include <reset-uclass.h>
65 #include "phy-rockchip-snps-pcie3.fw"
73 /* Deassert PCIe PMA output clamp mode */ in rockchip_p3phy_rk3568_init()
74 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9, in rockchip_p3phy_rk3568_init()
78 if (priv->is_bifurcation) { in rockchip_p3phy_rk3568_init()
79 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON6, in rockchip_p3phy_rk3568_init()
81 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON1, in rockchip_p3phy_rk3568_init()
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H A Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on drivers/phy/rockchip/phy-rockchip-typec.c in Linux Kernel.
12 #include <generic-phy.h>
17 #include <asm-generic/io.h>
125 writel(0x830, tcphy->base + PMA_CMN_CTRL1); in tcphy_cfg_24m()
128 * The following PHY configuration assumes a 24 MHz reference in tcphy_cfg_24m()
131 writel(0x90, tcphy->base + XCVR_DIAG_LANE_FCM_EN_MGN(i)); in tcphy_cfg_24m()
132 writel(0x960, tcphy->base + TX_RCVDET_EN_TMR(i)); in tcphy_cfg_24m()
133 writel(0x30, tcphy->base + TX_RCVDET_ST_TMR(i)); in tcphy_cfg_24m()
136 rdata = readl(tcphy->base + CMN_DIAG_HSCLK_SEL); in tcphy_cfg_24m()
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/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_mcu_shared_reg.c1 // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
4 * (C) COPYRIGHT 2022-2023 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
28 /* Scaling factor in pre-allocating shared regions for suspend bufs and userios */
38 #define CSG_REG_SUSP_BUF_VPFN(reg, nr_susp_pages) (reg->start_pfn)
39 #define CSG_REG_PMOD_BUF_VPFN(reg, nr_susp_pages) (reg->start_pfn + nr_susp_pages)
40 #define CSG_REG_USERIO_VPFN(reg, csi, nr_susp_pages) (reg->start_pfn + 2 * (nr_susp_pages + csi))
51 * struct kbase_csg_shared_region - Wrapper object for use with a CSG on runtime
58 * covers the normal/P-mode suspend buffers, userio pages of the queues
74 if (kbdev->system_coherency == COHERENCY_NONE) in get_userio_mmu_flags()
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H A Dmali_kbase_csf.c1 // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
4 * (C) COPYRIGHT 2018-2023 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
62 * struct irq_idle_and_protm_track - Object that tracks the idle and protected mode
79 * kbasep_ctx_user_reg_page_mapping_term() - Terminate resources for USER Register Page.
85 struct kbase_device *kbdev = kctx->kbdev; in kbasep_ctx_user_reg_page_mapping_term()
87 if (unlikely(kctx->csf.user_reg.vma)) in kbasep_ctx_user_reg_page_mapping_term()
88 dev_err(kbdev->dev, "VMA for USER Register page exist on termination of ctx %d_%d", in kbasep_ctx_user_reg_page_mapping_term()
89 kctx->tgid, kctx->id); in kbasep_ctx_user_reg_page_mapping_term()
90 if (WARN_ON_ONCE(!list_empty(&kctx->csf.user_reg.link))) in kbasep_ctx_user_reg_page_mapping_term()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/
H A Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
23 - description:
24 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
25 The AUX and PMA registers are not part of this range, they are instead
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/OK3568_Linux_fs/u-boot/include/linux/usb/
H A Dphy-rockchip-usbdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
13 /* RK3588 USBDP PHY Register Definitions */
30 /* PMA CMN Registers */
/OK3568_Linux_fs/kernel/include/linux/phy/
H A Dphy-rockchip-usbdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
13 /* RK3588 USBDP PHY Register Definitions */
30 /* PMA CMN Registers */
/OK3568_Linux_fs/kernel/drivers/phy/samsung/
H A Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS PHY driver for Samsung SoC
18 #include <linux/phy/phy.h>
22 #include "phy-samsung-ufs.h"
24 #define for_each_phy_lane(phy, i) \ argument
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
157 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
200 /* Transmit inter-frame gap adjustment value */
216 #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
234 /* In-Band FCS enable (FCS not stripped) */
250 /* In-Band FCS enable (FCS not generated) */
254 /* Inter-frame gap adjustment enable */
276 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
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