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/OK3568_Linux_fs/kernel/drivers/staging/greybus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 To compile this code as a module, chose M here: the module
12 will be called gb-audio.ko
20 bridge from an APB-I2S port to a Unipro network.
22 To compile this code as a module, chose M here: the module
23 will be called gb-audio-codec.ko
32 To compile this code as a module, chose M here: the module
33 will be called gb-bootrom.ko
42 To compile this code as a module, chose M here: the module
43 will be called gb-camera.ko
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-mtk-ufs.txt1 MediaTek Universal Flash Storage (UFS) M-PHY binding
2 --------------------------------------------------------
4 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
5 Each UFS M-PHY node should have its own node.
7 To bind UFS M-PHY with UFS host controller, the controller node should
8 contain a phandle reference to UFS M-PHY node.
10 Required properties for UFS M-PHY nodes:
11 - compatible : Compatible list, contains the following controller:
12 "mediatek,mt8183-ufsphy" for ufs phy
14 - reg : Address and length of the UFS M-PHY register set.
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H A Dphy-mtk-tphy.txt1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and
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H A Dphy-rockchip-naneng-usb2.txt1 ROCKCHIP USB2.0 PHY WITH NANENG IP BLOCK
3 Required properties (phy (parent) node):
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rv1126-usb2phy"
6 - reg : the address offset of grf for usb-phy configuration.
7 - rockchip,grf : phandle to the syscon managing the "general register files"
8 - clocks : phandle + phy specifier pair, for the input clocks of phy.
9 - clock-names : input clocks name of phy.
10 - resets : phandle + reset specifier pairs.
11 - reset-names : reset names of phy.
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H A Dphy-mtk-xsphy.txt1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
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H A Dphy-rockchip-inno-usb2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy with inno IP block
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk1808-usb2phy
17 - rockchip,rk3128-usb2phy
18 - rockchip,rk3228-usb2phy
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_set_pwr_table_8852b.c19 s8 _halrf_avg_power_8852b(struct rf_info *rf, enum phl_phy_idx phy, s8 *value, s8 n) in _halrf_avg_power_8852b() argument
36 void _halrf_bub_sort_8852b(struct rf_info *rf, enum phl_phy_idx phy, s8 *data, u32 n) in _halrf_bub_sort_8852b() argument
45 for (i = n - 1; i >= 0; i--) { in _halrf_bub_sort_8852b()
63 bool halrf_set_power_by_rate_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy) in halrf_set_power_by_rate_to_struct_8852b() argument
65 struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; in halrf_set_power_by_rate_to_struct_8852b()
66 struct rtw_tpu_pwr_by_rate_info *rate = &tpu->rtw_tpu_pwr_by_rate_i; in halrf_set_power_by_rate_to_struct_8852b()
71 …rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK1, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
72 …rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK2, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
73 …rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK5_5, 0, 0… in halrf_set_power_by_rate_to_struct_8852b()
74 …rate->pwr_by_rate_lgcy[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0)… in halrf_set_power_by_rate_to_struct_8852b()
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_set_pwr_table_8852b.c19 s8 _halrf_avg_power_8852b(struct rf_info *rf, enum phl_phy_idx phy, s8 *value, s8 n) in _halrf_avg_power_8852b() argument
36 void _halrf_bub_sort_8852b(struct rf_info *rf, enum phl_phy_idx phy, s8 *data, u32 n) in _halrf_bub_sort_8852b() argument
45 for (i = n - 1; i >= 0; i--) { in _halrf_bub_sort_8852b()
63 bool halrf_set_power_by_rate_to_struct_8852b(struct rf_info *rf, enum phl_phy_idx phy) in halrf_set_power_by_rate_to_struct_8852b() argument
65 struct rtw_tpu_info *tpu = &rf->hal_com->band[phy].rtw_tpu_i; in halrf_set_power_by_rate_to_struct_8852b()
66 struct rtw_tpu_pwr_by_rate_info *rate = &tpu->rtw_tpu_pwr_by_rate_i; in halrf_set_power_by_rate_to_struct_8852b()
71 …rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK1, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
72 …rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK2, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
73 …rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK5_5, 0, 0… in halrf_set_power_by_rate_to_struct_8852b()
74 …rate->pwr_by_rate_lgcy[3] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK11, 0, 0)… in halrf_set_power_by_rate_to_struct_8852b()
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/OK3568_Linux_fs/kernel/drivers/char/tpm/
H A Dtpm_tis_spi_main.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Christophe Ricard <christophe-h.ricard@st.com>
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
46 * [1] https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
48 static int tpm_tis_spi_flow_control(struct tpm_tis_spi_phy *phy, in tpm_tis_spi_flow_control() argument
51 struct spi_message m; in tpm_tis_spi_flow_control() local
54 if ((phy->iobuf[3] & 0x01) == 0) { in tpm_tis_spi_flow_control()
57 spi_xfer->len = 1; in tpm_tis_spi_flow_control()
58 spi_message_init(&m); in tpm_tis_spi_flow_control()
59 spi_message_add_tail(spi_xfer, &m); in tpm_tis_spi_flow_control()
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/OK3568_Linux_fs/kernel/drivers/usb/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
26 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
35 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
39 USB-On-The-Go transceiver working with the OMAP OTG controller.
45 will be called phy-isp1301-omap.
48 tristate "Keystone USB PHY Driver"
52 Enable this to support Keystone USB phy. This driver provides
53 interface to interact with USB 2.0 and USB 3.0 PHY that is part
58 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
62 built-in with usb ip or which are autonomous and doesn't require any
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/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Dinno_mipi_phy.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
18 #include <dm/uclass-id.h>
28 /* Innosilicon MIPI D-PHY registers */
257 writel(val, inno->regs + reg); in inno_write()
262 return readl(inno->regs + reg); in inno_read()
280 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
281 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
282 timing->clkpre = 8 * period; in mipi_dphy_timing_get_default()
283 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
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H A Drockchip-inno-hdmi-phy.c2 * SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <clk-uclass.h>
22 #include <linux/media-bus-format.h>
227 /* global variables are used to pass reource from phy drivers to clk driver */
322 /* tmdsclk bias-clk bias-data voltage-clk voltage-data pre-emphasis-data */
347 writel(val, inno->regs + (reg * 4)); in inno_write()
354 val = readl(inno->regs + (reg * 4)); in inno_read()
375 switch (inno->bus_width) { in inno_hdmi_phy_get_tmdsclk()
414 printf("%s: no misc-device found\n", __func__); in rk_get_cpu_version()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy_clk.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk-provider.h>
12 struct sun8i_hdmi_phy *phy; member
23 unsigned long rate = req->rate; in sun8i_phy_clk_determine_rate()
49 abs(rate - rounded / i) < in sun8i_phy_clk_determine_rate()
50 abs(rate - best_rate / best_div)) { in sun8i_phy_clk_determine_rate()
61 req->rate = best_rate / best_div; in sun8i_phy_clk_determine_rate()
62 req->best_parent_rate = best_rate; in sun8i_phy_clk_determine_rate()
63 req->best_parent_hw = best_parent; in sun8i_phy_clk_determine_rate()
74 regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, &reg); in sun8i_phy_clk_recalc_rate()
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/OK3568_Linux_fs/kernel/drivers/phy/marvell/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Marvell platforms
6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
46 Enable this to support Marvell A3700 UTMI PHY driver.
77 tristate "Marvell USB HSIC 28nm PHY Driver"
81 Enable this to support Marvell USB HSIC PHY driver for Marvell
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/OK3568_Linux_fs/u-boot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c6 * SPDX-License-Identifier: GPL-2.0+
43 * Due to missing documentaion of HDMI PHY, we know correct in sunxi_dw_hdmi_get_divider()
44 * settings only for following four PHY dividers. Select one in sunxi_dw_hdmi_get_divider()
59 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_phy_init() local
65 * HDMI PHY settings are taken as-is from Allwinner BSP code. in sunxi_dw_hdmi_phy_init()
68 writel(0, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
69 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
72 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
74 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
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/OK3568_Linux_fs/kernel/drivers/phy/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Mediatek devices
6 tristate "MediaTek T-PHY Driver"
11 Say 'Y' here to add support for MediaTek T-PHY driver,
13 SATA, and meanwhile supports two version T-PHY which have
14 different banks layout, the T-PHY with shared banks between
15 multi-ports is first version, otherwise is second version,
19 tristate "MediaTek UFS M-PHY driver"
24 Support for UFS M-PHY on MediaTek chipsets.
25 Enable this to provide vendor-specific probing,
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm IPQ4019 USB PHY driver"
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
29 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
36 tristate "Qualcomm PCIe Gen2 PHY Driver"
40 Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
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/OK3568_Linux_fs/u-boot/drivers/net/
H A Dsmc911x.c6 * SPDX-License-Identifier: GPL-2.0+
25 uchar *m = dev->enetaddr; in smc911x_handle_mac_address() local
27 addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24); in smc911x_handle_mac_address()
28 addrh = m[4] | (m[5] << 8); in smc911x_handle_mac_address()
32 printf(DRIVERNAME ": MAC %pM\n", m); in smc911x_handle_mac_address()
36 u8 phy, u8 reg, u16 *val) in smc911x_eth_phy_read() argument
41 smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | in smc911x_eth_phy_read()
53 u8 phy, u8 reg, u16 val) in smc911x_eth_phy_write() argument
60 phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); in smc911x_eth_phy_write()
97 if ((timeout--) == 0) in smc911x_phy_configure()
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/OK3568_Linux_fs/kernel/drivers/net/fddi/skfp/
H A Dsmt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #define m_fc(mb) ((mb)->sm_data[0])
55 static int phy_index(struct s_smc *smc, int phy);
57 static int phy_con_resource_index(struct s_smc *smc, int phy);
82 static void smt_fill_lem(struct s_smc *smc, struct smt_p_lem *lem, int phy);
111 return(*(short *)(&addr->a[0]) == in is_my_addr()
112 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[0]) in is_my_addr()
113 && *(short *)(&addr->a[2]) == in is_my_addr()
114 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[2]) in is_my_addr()
115 && *(short *)(&addr->a[4]) == in is_my_addr()
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/OK3568_Linux_fs/kernel/drivers/scsi/bfa/
H A Dbfa_ioc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
31 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \
33 #define bfa_ioc_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->ioc_timer)
36 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->hb_timer, \
38 #define bfa_hb_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->hb_timer)
55 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
57 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
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/OK3568_Linux_fs/output/sessions/2025-06-06_01-57-56/
H A D10-kernel-build_2025-06-06_01-57-58.log
H A Dbuild_2025-06-06_01-57-58.log
H A D10-kernel-build.log
H A Dbuild.log
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi-phy.c16 #include <linux/clk-provider.h>
24 #include <linux/nvmem-consumer.h>
26 #include <linux/phy/phy.h>
173 struct phy *phy; member
348 /* tmdsclk bias-clk bias-data voltage-clk voltage-data pre-emphasis-data */
378 regmap_write(inno->regmap, reg * 4, val); in inno_write()
385 regmap_read(inno->regmap, reg * 4, &val); in inno_read()
393 regmap_update_bits(inno->regmap, reg * 4, mask, val); in inno_update_bits()
398 int bus_width = phy_get_bus_width(inno->phy); in inno_hdmi_phy_get_tmdsclk()
432 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_hardirq()
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