Searched +full:jz4740 +full:- +full:watchdog (Results 1 – 16 of 16) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#11 Documentation/mips/ingenic-tcu.rst.14 - Paul Cercueil <paul@crapouillou.net>21 - ingenic,jz4740-tcu22 - ingenic,jz4725b-tcu23 - ingenic,jz4770-tcu24 - ingenic,jz4780-tcu25 - ingenic,x1000-tcu[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * JZ4740 Watchdog driver7 #include <linux/mfd/ingenic-tcu.h>13 #include <linux/watchdog.h>29 "Watchdog cannot be stopped once started (default="35 "Watchdog heartbeat period in seconds from 1 to "50 regmap_write(drvdata->map, TCU_REG_WDT_TCNT, 0); in jz4740_wdt_ping()59 u16 timeout_value = (u16)(drvdata->clk_rate * new_timeout); in jz4740_wdt_set_timeout()62 regmap_read(drvdata->map, TCU_REG_WDT_TCER, &tcer); in jz4740_wdt_set_timeout()63 regmap_write(drvdata->map, TCU_REG_WDT_TCER, 0); in jz4740_wdt_set_timeout()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only4 # Watchdog device configuration7 menuconfig WATCHDOG config8 bool "Watchdog Timer Support"11 character special file /dev/watchdog with major number 10 and minor12 number 130 using mknod ("man mknod"), you will get a watchdog, i.e.:16 on-line as fast as possible after a lock-up. There's both a watchdog18 reboot the machine) and a driver for hardware watchdog boards, which21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.23 The watchdog is usually used together with the watchdog daemon[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/jz4740-cgu.h>3 #include <dt-bindings/clock/ingenic,tcu.h>6 #address-cells = <1>;7 #size-cells = <1>;8 compatible = "ingenic,jz4740";11 #address-cells = <1>;12 #size-cells = <0>;16 compatible = "ingenic,xburst-mxu1.0";20 clock-names = "cpu";[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/jz4725b-cgu.h>3 #include <dt-bindings/clock/ingenic,tcu.h>6 #address-cells = <1>;7 #size-cells = <1>;11 #address-cells = <1>;12 #size-cells = <0>;16 compatible = "ingenic,xburst-mxu1.0";20 clock-names = "cpu";24 cpuintc: interrupt-controller {[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/jz4770-cgu.h>3 #include <dt-bindings/clock/ingenic,tcu.h>6 #address-cells = <1>;7 #size-cells = <1>;11 #address-cells = <1>;12 #size-cells = <0>;16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";20 clock-names = "cpu";24 cpuintc: interrupt-controller {[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/jz4780-cgu.h>3 #include <dt-bindings/clock/ingenic,tcu.h>4 #include <dt-bindings/dma/jz4780-dma.h>7 #address-cells = <1>;8 #size-cells = <1>;12 #address-cells = <1>;13 #size-cells = <0>;17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";21 clock-names = "cpu";[all …]
1 .. SPDX-License-Identifier: GPL-2.07 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all14 - JZ4725B introduced a separate channel, called Operating System Timer15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is16 64-bit.18 - Each one of the TCU channels has its own clock, which can be reparented to three21 - The watchdog and OST hardware blocks also feature a TCSR register with the same23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and26 - Each TCU channel works in one of two modes:[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include <linux/clk-provider.h>10 #include <linux/mfd/ingenic-tcu.h>16 #include <dt-bindings/clock/ingenic,tcu.h>18 /* 8 channels max + watchdog + OST */22 #define pr_fmt(fmt) "ingenic-tcu-clk: " fmt67 const struct ingenic_tcu_clk_info *info = tcu_clk->info; in ingenic_tcu_enable()68 struct ingenic_tcu *tcu = tcu_clk->tcu; in ingenic_tcu_enable()70 regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit)); in ingenic_tcu_enable()78 const struct ingenic_tcu_clk_info *info = tcu_clk->info; in ingenic_tcu_disable()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only44 This clock should be battery-backed, so that it reads the correct45 time when the system boots from a power-off state. Otherwise, your132 once-per-second update interrupts, used for synchronization.150 will be called rtc-test.164 will be called rtc-88pm860x.174 will be called rtc-88pm80x.178 tristate "Abracon AB-RTCMC-32.768kHz-B5ZE-S3"181 AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip.184 will be called rtc-ab-b5ze-s3.[all …]
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
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