| /OK3568_Linux_fs/kernel/drivers/clocksource/ |
| H A D | timer-microchip-pit64b.c | 54 * @gclk: PIT64B's generic clock
60 struct clk *gclk; member
165 clk_disable_unprepare(timer->gclk); in mchp_pit64b_clkevt_suspend()
175 clk_prepare_enable(timer->gclk); in mchp_pit64b_clkevt_resume()
210 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
211 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
212 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
215 * This function, first tries to use GCLK by requesting the desired rate from
217 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
227 * | |-->gclk -->|-->| | +---------+ +-----+ |
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| /OK3568_Linux_fs/kernel/sound/soc/atmel/ |
| H A D | mchp-i2s-mcc.c | 234 struct clk *gclk; member
425 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate, in mchp_i2s_mcc_config_divs()
429 dev_err(dev->dev, "gclk error for rate %lu: %d", in mchp_i2s_mcc_config_divs()
433 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n", in mchp_i2s_mcc_config_divs()
461 best_clk == dev->pclk ? "pclk" : "gclk", in mchp_i2s_mcc_config_divs()
469 if (best_clk == dev->gclk) in mchp_i2s_mcc_config_divs()
657 ret = clk_set_rate(dev->gclk, rate); in mchp_i2s_mcc_hw_params()
660 "unable to set rate %lu to GCLK: %d\n", in mchp_i2s_mcc_hw_params()
665 ret = clk_prepare(dev->gclk); in mchp_i2s_mcc_hw_params()
667 dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret); in mchp_i2s_mcc_hw_params()
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| H A D | atmel-classd.c | 31 struct clk *gclk; member
130 err = clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_startup()
365 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_hw_params()
367 ret = clk_set_rate(dd->gclk, sample_rates[best].gclk_rate); in atmel_classd_cpu_dai_hw_params()
377 return clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_hw_params()
387 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_shutdown()
553 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_classd_probe()
554 if (IS_ERR(dd->gclk)) { in atmel_classd_probe()
555 ret = PTR_ERR(dd->gclk); in atmel_classd_probe()
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| H A D | atmel-i2s.c | 197 struct clk *gclk; member
295 if (!dev->gclk) { in atmel_i2s_get_gck_param()
442 clk_disable_unprepare(dev->gclk); in atmel_i2s_switch_mck_generator()
452 ret = clk_set_rate(dev->gclk, gclk_rate); in atmel_i2s_switch_mck_generator()
456 ret = clk_prepare_enable(dev->gclk); in atmel_i2s_switch_mck_generator()
575 if (!dev->gclk) in atmel_i2s_sama5d2_mck_init()
589 return clk_set_parent(muxclk, dev->gclk); in atmel_i2s_sama5d2_mck_init()
661 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in atmel_i2s_probe()
662 if (IS_ERR(dev->gclk)) { in atmel_i2s_probe()
663 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER) in atmel_i2s_probe()
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| H A D | mchp-spdiftx.c | 197 struct clk *gclk; member
491 clk_disable_unprepare(dev->gclk); in mchp_spdiftx_hw_params()
494 ret = clk_set_rate(dev->gclk, params_rate(params) * in mchp_spdiftx_hw_params()
498 "unable to change gclk rate to: rate %u * ratio %u\n", in mchp_spdiftx_hw_params()
502 ret = clk_prepare_enable(dev->gclk); in mchp_spdiftx_hw_params()
504 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdiftx_hw_params()
508 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, in mchp_spdiftx_hw_params()
528 clk_disable_unprepare(dev->gclk); in mchp_spdiftx_hw_free()
811 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in mchp_spdiftx_probe()
812 if (IS_ERR(dev->gclk)) { in mchp_spdiftx_probe()
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| H A D | atmel-pdmic.c | 31 struct clk *gclk; member
111 ret = clk_prepare_enable(dd->gclk); in atmel_pdmic_cpu_dai_startup()
117 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_startup()
141 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_shutdown()
406 gclk_rate = clk_get_rate(dd->gclk); in atmel_pdmic_cpu_dai_hw_params()
531 u32 clk_min_rate = (u32)(clk_get_rate(dd->gclk) >> 8); in atmel_pdmic_get_sample_rate()
606 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_pdmic_probe()
607 if (IS_ERR(dd->gclk)) { in atmel_pdmic_probe()
608 ret = PTR_ERR(dd->gclk); in atmel_pdmic_probe()
613 /* The gclk clock frequency must always be three times in atmel_pdmic_probe()
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| H A D | mchp-spdifrx.c | 239 struct clk *gclk; member
449 clk_disable_unprepare(dev->gclk); in mchp_spdifrx_hw_params()
452 ret = clk_set_min_rate(dev->gclk, params_rate(params) * in mchp_spdifrx_hw_params()
456 "unable to set gclk min rate: rate %u * ratio %u + 1\n", in mchp_spdifrx_hw_params()
460 ret = clk_prepare_enable(dev->gclk); in mchp_spdifrx_hw_params()
462 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdifrx_hw_params()
467 dev_dbg(dev->dev, "GCLK range min set to %d\n", in mchp_spdifrx_hw_params()
479 clk_disable_unprepare(dev->gclk); in mchp_spdifrx_hw_free()
696 rate = clk_get_rate(dev->gclk); in mchp_spdifrx_rate_get()
908 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in mchp_spdifrx_probe()
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | emev2.dtsi | 78 compatible = "renesas,emev2-smu-gclk";
90 compatible = "renesas,emev2-smu-gclk";
127 compatible = "renesas,emev2-smu-gclk";
133 compatible = "renesas,emev2-smu-gclk";
139 compatible = "renesas,emev2-smu-gclk";
145 compatible = "renesas,emev2-smu-gclk";
151 compatible = "renesas,emev2-smu-gclk";
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| H A D | sama5d2.dtsi | 391 clock-names = "t0_clk", "gclk", "slow_clk";
401 clock-names = "t0_clk", "gclk", "slow_clk";
429 clock-names = "pclk", "gclk";
720 clock-names = "pclk", "gclk";
1110 clock-names = "pclk", "gclk";
1126 clock-names = "pclk", "gclk";
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | renesas,emev2-smu.txt | 32 - compatible: Should be "renesas,emev2-smu-gclk"
47 compatible = "renesas,emev2-smu-gclk";
93 compatible = "renesas,emev2-smu-gclk";
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/ |
| H A D | atmel-classd.txt | 16 Required elements: "pclk" and "gclk".
47 clock-names = "pclk", "gclk";
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| H A D | atmel-pdmic.txt | 17 - "gclk" generated clock
47 clock-names = "pclk", "gclk";
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| H A D | mchp,spdiftx.yaml | 37 - const: gclk
72 clock-names = "pclk", "gclk";
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| H A D | mchp-i2s-mcc.txt | 16 - "gclk" (generated clock) Optional (1).
40 clock-names = "pclk", "gclk";
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| H A D | mchp,spdifrx.yaml | 37 - const: gclk
72 clock-names = "pclk", "gclk";
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| H A D | atmel-i2s.txt | 17 - "gclk" (generated clock) Optional (1).
43 clock-names = "pclk", "gclk", "muxclk";
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | nv40.c | 149 int gclk = cstate->domain[nv_clk_src_core]; in nv40_clk_calc() local
155 ret = nv40_clk_calc_pll(clk, 0x004000, gclk, in nv40_clk_calc()
169 if (sclk && sclk != gclk) { in nv40_clk_calc()
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| /OK3568_Linux_fs/kernel/drivers/rk_nand/ |
| H A D | rk_nand_base.c | 333 g_nandc_info[id].gclk = devm_clk_get(&pdev->dev, "g_clk_nandc"); in rknand_probe()
350 if (!(IS_ERR(g_nandc_info[id].gclk))) in rknand_probe()
351 clk_prepare_enable(g_nandc_info[id].gclk); in rknand_probe()
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| H A D | rk_nand_base.h | 17 struct clk *gclk; /* flash clk gate*/ member
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| /OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc8xx/ |
| H A D | speed.c | 26 * If for some reason measuring the gclk frequency won't in get_clocks()
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| H A D | Kconfig | 29 int "CPU GCLK Frequency"
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| /OK3568_Linux_fs/u-boot/drivers/clk/at91/ |
| H A D | Kconfig | 43 clock is the generic clock (GCLK) and is managed by
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| /OK3568_Linux_fs/kernel/drivers/clk/at91/ |
| H A D | clk-generated.c | 42 pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", in clk_generated_enable()
195 pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", in clk_generated_determine_rate()
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| /OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc86xx/ |
| H A D | speed.c | 86 * (Approx. GCLK frequency in Hz)
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| /OK3568_Linux_fs/kernel/drivers/clk/renesas/ |
| H A D | clk-emev2.c | 98 CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
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