| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpufreq/ |
| H A D | cpufreq-qcom-hw.txt | 8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
27 each frequency domain.
28 - reg-names
31 Definition: Frequency domain name i.e.
32 "freq-domain0", "freq-domain1".
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| /OK3568_Linux_fs/kernel/include/linux/ |
| H A D | energy_model.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * em_perf_state - Performance state of a performance domain
16 * @power: The power consumed at this level, in milli-watts (by 1 CPU or
29 * em_perf_domain - Performance domain
32 * @milliwatts: Flag indicating the power values are in milli-Watts
34 * @cpus: Cpumask covering the CPUs of the domain. It's here
39 * In case of CPU device, a "performance domain" represents a group of CPUs
40 * whose performance is scaled together. All CPUs of a performance domain
41 * must have the same micro-architecture. Performance domains often have
42 * a 1-to-1 mapping with CPUFreq policies. In case of other devices the @cpus
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| /OK3568_Linux_fs/kernel/drivers/firmware/arm_scmi/ |
| H A D | perf.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 ARM Ltd.
8 #define pr_fmt(fmt) "SCMI Notifications PERF - " fmt
13 #include <linux/io-64-nonatomic-hi-lo.h>
64 __le32 domain; member
69 __le32 domain; member
80 __le32 domain; member
85 __le32 domain; member
114 __le32 domain; member
186 ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0, in scmi_perf_attributes_get()
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| /OK3568_Linux_fs/kernel/kernel/power/ |
| H A D | energy_model.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018-2020, Arm ltd.
27 return (dev->bus == &cpu_subsys); in _is_cpu_device()
38 snprintf(name, sizeof(name), "ps:%lu", ps->frequency); in em_debug_create_ps()
40 /* Create per-ps directory */ in em_debug_create_ps()
42 debugfs_create_ulong("frequency", 0444, d, &ps->frequency); in em_debug_create_ps()
43 debugfs_create_ulong("power", 0444, d, &ps->power); in em_debug_create_ps()
44 debugfs_create_ulong("cost", 0444, d, &ps->cost); in em_debug_create_ps()
49 seq_printf(s, "%*pbl\n", cpumask_pr_args(to_cpumask(s->private))); in em_debug_cpus_show()
57 struct em_perf_domain *pd = s->private; in em_debug_units_show()
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ |
| H A D | dfs_pattern_detector.c | 25 * struct radar_types - contains array of patterns defined for one DFS domain
26 * @domain: DFS regulatory domain
38 #define PPB_THRESH_RATE(PPB, RATE) ((PPB * RATE + 100 - RATE) / 100)
43 #define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100)
49 (PRF2PRI(PMAX) - PRI_TOLERANCE), \
54 /* radar types as defined by ETSI EN-301-893 v1.5.1 */
74 PMIN - PRI_TOLERANCE, \
106 PMIN - PRI_TOLERANCE, \
135 * get_dfs_domain_radar_types() - get radar types for a given DFS domain
136 * @param domain DFS domain
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | base.c | 42 u8 pstate, u8 domain, u32 input) in nvkm_clk_adjust() argument
44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
62 if (subd && boostS.domain == domain) { in nvkm_clk_adjust()
76 * C-States
82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid() local
83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid()
86 while (domain && domain->name != nv_clk_src_max) { in nvkm_cstate_valid()
87 if (domain->flags & NVKM_CLK_DOM_FLAG_VPSTATE) { in nvkm_cstate_valid()
88 u32 freq = cstate->domain[domain->name]; in nvkm_cstate_valid() local
89 switch (clk->boost_mode) { in nvkm_cstate_valid()
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| H A D | gf100.c | 33 u32 freq; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
107 return device->crystal; in read_div()
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| H A D | nv50.c | 34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll_src()
127 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_ref()
128 struct nvkm_device *device = subdev->device; in read_pll_ref()
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| H A D | gk104.c | 33 u32 freq; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
77 sclk = device->crystal; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
147 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
192 struct nvkm_subdev *subdev = &clk->base.subdev; in gk104_clk_read()
193 struct nvkm_device *device = subdev->device; in gk104_clk_read()
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| /OK3568_Linux_fs/kernel/drivers/cpufreq/ |
| H A D | qcom-cpufreq-hw.c | 1 // SPDX-License-Identifier: GPL-2.0
50 dev = get_cpu_device(policy->cpu); in qcom_cpufreq_set_bw()
52 return -ENODEV; in qcom_cpufreq_set_bw()
76 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz); in qcom_cpufreq_update_opp()
86 struct qcom_cpufreq_data *data = policy->driver_data; in qcom_cpufreq_hw_target_index()
87 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; in qcom_cpufreq_hw_target_index()
88 unsigned long freq = policy->freq_table[index].frequency; in qcom_cpufreq_hw_target_index() local
90 writel_relaxed(index, data->base + soc_data->reg_perf_state); in qcom_cpufreq_hw_target_index()
93 qcom_cpufreq_set_bw(policy, freq); in qcom_cpufreq_hw_target_index()
109 data = policy->driver_data; in qcom_cpufreq_hw_get()
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| H A D | scmi-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
34 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_get_rate()
38 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate()
45 * perf_ops->freq_set is not a synchronous, the actual OPP change will
52 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target()
53 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target() local
55 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target()
61 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch()
63 if (!perf_ops->freq_set(ph, priv->domain_id, in scmi_cpufreq_fast_switch()
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| /OK3568_Linux_fs/kernel/Documentation/power/ |
| H A D | energy-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 -----------
12 subsystems willing to use that information to make energy-aware decisions.
18 each and every client subsystem to re-implement support for each and every
23 The figure below depicts an example of drivers (Arm-specific here, but the
27 +---------------+ +-----------------+ +---------------+
29 +---------------+ +-----------------+ +---------------+
32 +---------+ | +---------+
35 +---------------------+
38 +---------------------+
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| H A D | opp.rst | 5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
30 the device will support per domain are called Operating Performance Points or
41 - {300000000, 1000000}
42 - {800000000, 1200000}
43 - {1000000000, 1300000}
46 ----------------------------------------
57 (users) -> registers a set of default OPPs -> (library)
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-keystone/ |
| H A D | cmd_clock.c | 4 * (C) Copyright 2012-2014
7 * SPDX-License-Identifier: GPL-2.0+
70 unsigned long freq; in do_getclk_cmd() local
77 freq = ks_clk_get_rate(clk); in do_getclk_cmd()
78 if (freq) in do_getclk_cmd()
79 printf("clock index [%d] - frequency %lu\n", clk, freq); in do_getclk_cmd()
107 printf("psc_enable_module(%d) - %s\n", psc_module, in do_psc_cmd()
114 printf("psc_disable_module(%d) - %s\n", psc_module, in do_psc_cmd()
119 if (strcmp(argv[2], "domain") == 0) { in do_psc_cmd()
121 printf("psc_disable_domain(%d) - %s\n", psc_module, in do_psc_cmd()
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| /OK3568_Linux_fs/kernel/arch/arm/mach-omap2/ |
| H A D | omap_opp_data.h | 4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/
33 * struct omap_opp_def - OMAP OPP Definition
34 * @hwmod_name: Name of the hwmod for this domain
35 * @freq: Frequency in hertz corresponding to this OPP
37 * @default_available: True/false - is this OPP available by default
40 * pairs that the device will support per voltage domain. This is called
43 * domain, you can have a set of {frequency, voltage} pairs and this is denoted
47 * which belongs to a voltage domain may define their own set of OPPs on top
48 * of this - but this is handled by the appropriate driver.
53 unsigned long freq; member
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/core/ |
| H A D | rtw_rf.c | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
222 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; in rtw_get_scch_by_cch_offset()
228 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8; in rtw_get_scch_by_cch_offset()
233 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4; in rtw_get_scch_by_cch_offset()
238 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; in rtw_get_scch_by_cch_offset()
336 for (i = 0; i < c_chs_ent->ch_num; i++) in rtw_get_op_chs_by_cch_bw()
337 if (cch == *(c_chs_ent->chs + i)) in rtw_get_op_chs_by_cch_bw()
340 if (i == c_chs_ent->ch_num) { in rtw_get_op_chs_by_cch_bw()
345 *op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i; in rtw_get_op_chs_by_cch_bw()
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/core/ |
| H A D | rtw_rf.c | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
222 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; in rtw_get_scch_by_cch_offset()
228 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8; in rtw_get_scch_by_cch_offset()
233 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4; in rtw_get_scch_by_cch_offset()
238 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; in rtw_get_scch_by_cch_offset()
336 for (i = 0; i < c_chs_ent->ch_num; i++) in rtw_get_op_chs_by_cch_bw()
337 if (cch == *(c_chs_ent->chs + i)) in rtw_get_op_chs_by_cch_bw()
340 if (i == c_chs_ent->ch_num) { in rtw_get_op_chs_by_cch_bw()
345 *op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i; in rtw_get_op_chs_by_cch_bw()
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/core/ |
| H A D | rtw_rf.c | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
222 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; in rtw_get_scch_by_cch_offset()
228 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8; in rtw_get_scch_by_cch_offset()
233 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4; in rtw_get_scch_by_cch_offset()
238 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; in rtw_get_scch_by_cch_offset()
336 for (i = 0; i < c_chs_ent->ch_num; i++) in rtw_get_op_chs_by_cch_bw()
337 if (cch == *(c_chs_ent->chs + i)) in rtw_get_op_chs_by_cch_bw()
340 if (i == c_chs_ent->ch_num) { in rtw_get_op_chs_by_cch_bw()
345 *op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i; in rtw_get_op_chs_by_cch_bw()
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| /OK3568_Linux_fs/kernel/drivers/firmware/ |
| H A D | arm_scpi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * provides a mechanism for inter-processor communication between SCP's
11 * various power domain DVFS including the core/cluster, certain system
207 -1, /* GET_CLOCK_INFO */
216 -1, /* SET_DEVICE_PWR_STATE */
217 -1, /* GET_DEVICE_PWR_STATE */
259 * The SCP firmware only executes in little-endian mode, so any buffers
260 * shared through SCPI should have their contents converted to little-endian
301 u8 domain; member
305 __le32 freq; member
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| /OK3568_Linux_fs/kernel/net/wireless/ |
| H A D | reg.h | 7 * Copyright 2008-2011 Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
40 * regulatory_hint_indoor - hint operation in indoor env. or not
48 * regulatory_netlink_notify - notify on released netlink socket
69 * regulatory_hint_found_beacon - hints a beacon was found on a channel
77 * world roaming -- when we do not know our current location. This is
79 * 1-11 are already enabled by the world regulatory domain; and on
80 * non-radar 5 GHz channels.
84 * set the wiphy->disable_beacon_hints to true.
91 * regulatory_hint_country_ie - hints a country IE as a regulatory domain
117 * regulatory_hint_disconnect - informs all devices have been disconnected
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| H A D | reg.c | 2 * Copyright 2002-2005, Instant802 Networks, Inc.
3 * Copyright 2005-2006, Devicescape Software, Inc.
5 * Copyright 2008-2011 Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
6 * Copyright 2013-2014 Intel Mobile Communications GmbH
8 * Copyright (C) 2018 - 2019 Intel Corporation
28 * determine which regulatory domain it should be operating under, then
29 * looking up the allowable channels in a driver-local table and finally
42 * Note: When number of rules --> infinity we will not be able to
63 #include "rdev-ops.h"
68 * channels allowed by the current regulatory domain.
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/core/ |
| H A D | rtw_rf.c | 3 * Copyright(c) 2007 - 2017 Realtek Corporation.
221 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; in rtw_get_scch_by_cch_offset()
227 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8; in rtw_get_scch_by_cch_offset()
232 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4; in rtw_get_scch_by_cch_offset()
237 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; in rtw_get_scch_by_cch_offset()
355 for (i = 0; i < c_chs_ent->ch_num; i++) in rtw_get_op_chs_by_cch_bw()
356 if (cch == *(c_chs_ent->chs + i)) in rtw_get_op_chs_by_cch_bw()
359 if (i == c_chs_ent->ch_num) { in rtw_get_op_chs_by_cch_bw()
364 *op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i; in rtw_get_op_chs_by_cch_bw()
365 *op_ch_num = op_chs_ent->ch_num; in rtw_get_op_chs_by_cch_bw()
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| /OK3568_Linux_fs/kernel/drivers/gpu/arm/mali400/mali/platform/arm/ |
| H A D | juno_opp.c | 2 * Copyright (C) 2010, 2012-2017 ARM Limited. All rights reserved.
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
50 return -1; in init_juno_opps_from_scpi()
53 /* Hard coded for Juno. 2 is GPU domain */ in init_juno_opps_from_scpi()
54 sinfo = sops->dvfs_get_info(2); in init_juno_opps_from_scpi()
58 for (i = 0; i < sinfo->count; i++) { in init_juno_opps_from_scpi()
59 struct scpi_opp *e = &sinfo->opps[i]; in init_juno_opps_from_scpi()
61 MALI_DEBUG_PRINT(2, ("Mali OPP from SCPI: %u Hz @ %u mV\n", e->freq, e->m_volt)); in init_juno_opps_from_scpi()
63 dev_pm_opp_add(dev, e->freq, e->m_volt * 1000); in init_juno_opps_from_scpi()
78 return -EFAULT; in setup_opps()
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/ |
| H A D | sm8150.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-aoss-qmp.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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| /OK3568_Linux_fs/kernel/drivers/soc/qcom/ |
| H A D | cpr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
125 #define FUSE_REVISION_UNKNOWN (-1)
163 unsigned long freq; member
221 unsigned long freq; member
254 return !drv->loop_disabled; in cpr_is_allowed()
259 writel_relaxed(value, drv->base + offset); in cpr_write()
264 return readl_relaxed(drv->base + offset); in cpr_read()
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