| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/ |
| H A D | rockchip,rk3228-codec.txt | 18 clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
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| H A D | rockchip,rk3328-codec.yaml | 65 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
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| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | s3c2443.h | 33 #define SCLK_I2S1 19 macro
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| H A D | exynos7-clk.h | 117 #define SCLK_I2S1 25 macro
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| H A D | rk3188-cru-common.h | 32 #define SCLK_I2S1 76 macro
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| H A D | rk3228-cru.h | 28 #define SCLK_I2S1 81 macro
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| H A D | rk3128-cru.h | 29 #define SCLK_I2S1 81 macro
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| H A D | rv1108-cru.h | 26 #define SCLK_I2S1 76 macro
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| H A D | rk3328-cru.h | 31 #define SCLK_I2S1 42 macro
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| H A D | px30-cru.h | 22 #define SCLK_I2S1 20 macro
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | exynos7-clock.txt | 87 - sclk_i2s1
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| /OK3568_Linux_fs/u-boot/include/dt-bindings/clock/ |
| H A D | exynos7420-clk.h | 120 #define SCLK_I2S1 25 macro
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| H A D | rk3188-cru-common.h | 33 #define SCLK_I2S1 76 macro
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| H A D | rk3228-cru.h | 28 #define SCLK_I2S1 81 macro
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| H A D | rk3128-cru.h | 29 #define SCLK_I2S1 81 macro
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| H A D | rv1108-cru.h | 26 #define SCLK_I2S1 76 macro
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| H A D | rk3328-cru.h | 31 #define SCLK_I2S1 42 macro
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| H A D | px30-cru.h | 35 #define SCLK_I2S1 20 macro
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_px30.c | 434 case SCLK_I2S1: in px30_i2s_get_clk()
465 case SCLK_I2S1: in px30_i2s_set_clk()
496 return px30_i2s_get_clk(priv, SCLK_I2S1); in px30_i2s1_mclk_get_clk()
508 px30_i2s_set_clk(priv, SCLK_I2S1, hz); in px30_i2s1_mclk_set_clk()
1333 case SCLK_I2S1: in px30_clk_get_rate()
1419 case SCLK_I2S1: in px30_clk_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-s3c2443.c | 294 GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
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| H A D | clk-exynos7.c | 347 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
794 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3128.c | 369 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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| H A D | clk-rk3228.c | 435 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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| H A D | clk-rv1108.c | 522 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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| H A D | clk-rk3188.c | 553 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
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