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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/ti/
H A Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
H A Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
H A Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
105 * @clk: struct clk * of the DPLL to compute the rate for
107 * Compute the output rate for the OMAP4 DPLL represented by @clk.
109 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
127 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
H A Ddpll.c2 * OMAP DPLL clock support
153 * _register_dpll - low level registration of a DPLL clock
157 * Finalizes DPLL registration process. In case a failure (clk-ref or
221 * Initializes a DPLL x 2 clock from device tree data.
278 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
279 * @node: device node containing the DPLL info
280 * @ops: ops for the DPLL
281 * @ddt: DPLL data template to use
283 * Initializes a DPLL clock from device tree data.
326 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c105 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
152 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
154 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
155 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
157 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
162 dpll |= in psb_intel_crtc_mode_set()
167 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
173 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
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H A Doaktrail_crtc.c241 /* Enable the DPLL */ in oaktrail_crtc_dpms()
242 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
244 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
245 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
248 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
250 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
253 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
255 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
314 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
316 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
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H A Dmdfld_intel_display.c243 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
249 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
250 REG_READ(map->dpll); in mdfld_disable_crtc()
256 /* gating power of DPLL */ in mdfld_disable_crtc()
257 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
298 /* Enable the DPLL */ in mdfld_crtc_dpms()
299 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
302 /* When ungating power of DPLL, needs to wait 0.5us in mdfld_crtc_dpms()
306 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
311 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
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H A Dcdv_intel_display.c206 /* Unlike most Intel display engines, on Cedarview the DPLL registers
208 * DPLL reference clock is on in the DPLL control register, but before
209 * the DPLL is enabled in the DPLL control register.
260 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
662 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
665 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ in cdv_intel_crtc_mode_set()
666 dpll |= 3; in cdv_intel_crtc_mode_set()
668 /* dpll |= PLL_REF_INPUT_DREFCLK; */ in cdv_intel_crtc_mode_set()
679 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
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H A Dmdfld_device.c188 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
242 u32 dpll; in mdfld_restore_display_registers() local
249 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
274 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
275 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
280 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
282 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
284 /* When ungating power of DPLL, needs to wait 0.5us in mdfld_restore_display_registers()
286 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
287 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
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H A Dgma_display.c214 /* Enable the DPLL */ in gma_crtc_dpms()
215 temp = REG_READ(map->dpll); in gma_crtc_dpms()
217 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
218 REG_READ(map->dpll); in gma_crtc_dpms()
221 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
302 /* Disable DPLL */ in gma_crtc_dpms()
303 temp = REG_READ(map->dpll); in gma_crtc_dpms()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h49 * enum intel_dpll_id - possible DPLL ids
51 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
60 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
64 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
170 u32 dpll; member
181 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
184 * the DPLL.
216 * struct intel_shared_dpll_state - hold the DPLL atomic state
218 * This structure holds an atomic state for the DPLL, that can represent
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H A Dintel_dpll_mgr.c70 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
71 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
72 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
96 * intel_get_shared_dpll_by_id - get a DPLL given its id
101 * A pointer to the DPLL with @id
107 return &dev_priv->dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
111 * intel_get_shared_dpll_id - get the id of a DPLL
113 * @pll: the DPLL
122 long pll_idx = pll - dev_priv->dpll.shared_dplls; in intel_get_shared_dpll_id()
126 pll_idx >= dev_priv->dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
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/OK3568_Linux_fs/kernel/include/linux/clk/
H A Dti.h34 * struct dpll_data - DPLL registers and integration data
35 * @mult_div1_reg: register containing the DPLL M and N bitfields
36 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
37 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
40 * @control_reg: register containing the DPLL mode bitfield
41 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
52 * @max_rate: maximum clock rate for the DPLL
54 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
55 * @idlest_reg: register containing the DPLL idle status bitfield
56 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
H A Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
H A Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
65 * Voltage/DPLL ratios
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
[all …]
H A Dclkt2xxx_dpllcore.c3 * DPLL + CORE_CLK composite clock functions
15 * XXX The DPLL and CORE clocks should be split into two separate clock
46 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
80 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ in omap2_dpllcore_round_rate()
83 } else { /* DPLL clockout x 2 */ in omap2_dpllcore_round_rate()
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/clk/
H A DMakefile7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
9 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
10 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
11 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
12 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
16 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
17 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
18 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/
H A Dclocks-common.c58 /* SYS_CLKSEL - 1 to match the dpll param array indices */ in __get_sys_clk_index()
117 printf("Bypassing DPLL failed %x\n", base); in wait_for_bypass()
136 printf("DPLL locking failed for %x\n", base); in wait_for_lock()
212 u8 lock, char *dpll) in do_setup_dpll() argument
224 * The Dpll has already been locked by rom code using CH. in do_setup_dpll()
231 debug("\n %s Dpll locked, but not for ideal M = %d," in do_setup_dpll()
233 "N= %d" , dpll, params->m, params->n, in do_setup_dpll()
236 /* Dpll locked with ideal values for nominal opps. */ in do_setup_dpll()
237 debug("\n %s Dpll already locked with ideal" in do_setup_dpll()
238 "nominal opp values", dpll); in do_setup_dpll()
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-omap3/
H A Dclocks_omap3.h18 * and hence are defined here. All the other DPLL related values are
22 /* CORE DPLL */
32 /* PER DPLL */
40 /* MPU DPLL */
117 /* IVA DPLL */
194 /* CORE DPLL */
246 /* PER DPLL */
273 /* PER2 DPLL */
299 /* 36XX PER DPLL */
326 /* 36XX PER2 DPLL */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/OK3568_Linux_fs/kernel/drivers/ide/
H A Dhpt366.c71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
99 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
102 * with only the chip type and its specific base DPLL frequency, the highest
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
109 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
112 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
400 u8 dpll_clk; /* DPLL clock in MHz */
451 .dpll_clk = 0, /* no DPLL */
793 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
842 * hpt37x_calibrate_dpll - calibrate the DPLL
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/lib/
H A Dasm-offsets.c33 * - struct dpll in main()
191 /* DPLL */ in main()
192 DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); in main()
193 DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); in main()
194 DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); in main()
195 DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); in main()
196 DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); in main()
197 DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); in main()
198 DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); in main()
199 DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); in main()
/OK3568_Linux_fs/kernel/drivers/ata/
H A Dpata_hpt3x2n.c70 /* 66MHz DPLL clocks */
268 * We must use the DPLL for
304 /* See if we should use the DPLL */ in hpt3x2n_use_dpll()
317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
324 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
335 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
337 flags |= dpll; in hpt3x2n_qc_issue()
340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
377 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
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