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/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igc/
H A Digc_regs.h118 #define IGC_CRCERRS 0x04000 /* CRC Error Count - R/clr */
119 #define IGC_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
120 #define IGC_RXERRC 0x0400C /* Receive Error Count - R/clr */
121 #define IGC_MPC 0x04010 /* Missed Packet Count - R/clr */
122 #define IGC_SCC 0x04014 /* Single Collision Count - R/clr */
123 #define IGC_ECOL 0x04018 /* Excessive Collision Count - R/clr */
124 #define IGC_MCC 0x0401C /* Multiple Collision Count - R/clr */
125 #define IGC_LATECOL 0x04020 /* Late Collision Count - R/clr */
126 #define IGC_COLC 0x04028 /* Collision Count - R/clr */
127 #define IGC_RERC 0x0402C /* Receive Error Count - R/clr */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/e1000e/
H A Dregs.h32 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
121 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
122 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
123 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
124 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
125 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
126 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
127 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
128 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
129 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igb/
H A De1000_regs.h21 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
30 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
188 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
189 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
190 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
191 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
192 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
193 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
194 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
195 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/OK3568_Linux_fs/buildroot/dl/mpg123/
HDmpg123-1.25.15.tar.bz2mpg123-1.25.15/ mpg123-1.25.15/man1/ mpg123-1.25.15 ...
/OK3568_Linux_fs/u-boot/arch/x86/include/asm/arch-quark/
H A Dmsg_port.h109 #define msg_port_generic_clrsetbits(type, port, reg, clr, set) \ argument
112 & ~(clr)) | (set))
114 #define msg_port_clrbits(port, reg, clr) \ argument
115 msg_port_generic_clrsetbits(normal, port, reg, clr, 0)
118 #define msg_port_clrsetbits(port, reg, clr, set) \ argument
119 msg_port_generic_clrsetbits(normal, port, reg, clr, set)
121 #define msg_port_alt_clrbits(port, reg, clr) \ argument
122 msg_port_generic_clrsetbits(alt, port, reg, clr, 0)
125 #define msg_port_alt_clrsetbits(port, reg, clr, set) \ argument
126 msg_port_generic_clrsetbits(alt, port, reg, clr, set)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dhardware.h10 #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) argument
12 #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) argument
16 #define rk_clrsetreg(addr, clr, set) \ argument
17 writel((((clr) | (set)) << 16) | (set), addr)
18 #define rk_clrreg(addr, clr) writel((clr) << 16, addr) argument
/OK3568_Linux_fs/kernel/arch/m68k/math-emu/
H A Dfp_util.S70 2: clr.l %d0
99 clr.l %d1 | sign defaults to zero
109 clr.l (%a0)
116 clr.l (%a0)+
117 clr.l (%a0)+
118 clr.l (%a0)
142 clr.l (%a0) | low lword = 0
236 clr.b (%a0)
274 clr.l %d0
279 clr.w -(%a0)
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-rpc/
H A Dirq.c14 #define CLR 0x04 macro
39 writeb(mask, base + CLR); in iomd_irq_mask_ack()
75 unsigned int irq, clr, set; in rpc_init_irq() local
86 clr = IRQ_NOREQUEST; in rpc_init_irq()
90 clr |= IRQ_NOPROBE; in rpc_init_irq()
100 irq_modify_status(irq, clr, set); in rpc_init_irq()
108 irq_modify_status(irq, clr, set); in rpc_init_irq()
116 irq_modify_status(irq, clr, set); in rpc_init_irq()
123 irq_modify_status(irq, clr, set); in rpc_init_irq()
/OK3568_Linux_fs/kernel/arch/m68k/ifpsp060/src/
H A Ditest.S81 clr.l TESTCTR(%a6)
91 clr.l TESTCTR(%a6)
101 clr.l TESTCTR(%a6)
111 clr.l TESTCTR(%a6)
121 clr.l TESTCTR(%a6)
132 clr.l TESTCTR(%a6)
142 clr.l TESTCTR(%a6)
169 clr.l %d1
181 clr.l IREGS+0x8(%a6)
182 clr.l IREGS+0xc(%a6)
[all …]
/OK3568_Linux_fs/u-boot/board/samsung/odroid/
H A Dodroid.c96 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; in board_clock_init() local
152 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | in board_clock_init()
156 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init()
168 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); in board_clock_init()
171 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init()
224 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | in board_clock_init()
241 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init()
248 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | in board_clock_init()
264 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init()
271 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | in board_clock_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Datafb_utils.h85 " lsr.l #1,%1 ; jcc 1f ; clr.b (%0)+\n" in fb_memclear()
86 "1: lsr.l #1,%1 ; jcc 1f ; clr.w (%0)+\n" in fb_memclear()
87 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+\n" in fb_memclear()
88 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
96 " lsr.l #1,%2 ; jcc 1f ; clr.b (%0)+ ; subq.w #1,%1\n" in fb_memclear()
98 " clr.w (%0)+ ; subq.w #2,%1 ; jra 2f\n" in fb_memclear()
100 " clr.w (%0)+ ; subq.w #2,%1\n" in fb_memclear()
102 " lsr.l #1,%1 ; jcc 3f ; clr.l (%0)+\n" in fb_memclear()
103 "3: lsr.l #1,%1 ; jcc 4f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
105 "5: clr.l (%0)+; clr.l (%0)+ ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
[all …]
/OK3568_Linux_fs/kernel/include/trace/events/
H A Dthp.h49 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set),
50 TP_ARGS(addr, pte, clr, set),
54 __field(unsigned long, clr)
61 __entry->clr = clr;
66 …page update at addr 0x%lx and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, …
/OK3568_Linux_fs/kernel/arch/sparc/lib/
H A Dffs.S14 clr %o0
21 clr %o1 /* 2 */
25 1: clr %o2
31 clr %o3
34 clr %o4
40 clr %o5
/OK3568_Linux_fs/kernel/Documentation/admin-guide/
H A Dmono.rst5 (in the form of .exe files) without the need to use the mono CLR
11 1) You MUST FIRST install the Mono CLR support, either by downloading
21 Once the Mono CLR support has been installed, just check that
50 # Register support for .NET CLR binaries
53 # the Mono CLR runtime (usually /usr/local/bin/mono
55 echo ':CLR:M::MZ::/usr/bin/mono:' > /proc/sys/fs/binfmt_misc/register
/OK3568_Linux_fs/kernel/arch/m68k/ifpsp060/
H A Dos.S94 clr.l %d1 | return success
101 clr.l %d1 | return success
127 clr.l %d1 | return success
134 clr.l %d1 | return success
151 clr.l %d0 | clear whole longword
152 clr.l %d1 | assume success
187 clr.l %d1 | assume success
188 clr.l %d0 | clear whole longword
223 clr.l %d1 | assume success
245 clr.l %d1 | assume success
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dconsole_rotate.c15 static int console_set_row_1(struct udevice *dev, uint row, int clr) in console_set_row_1() argument
31 *dst++ = clr; in console_set_row_1()
40 *dst++ = clr; in console_set_row_1()
49 *dst++ = clr; in console_set_row_1()
147 static int console_set_row_2(struct udevice *dev, uint row, int clr) in console_set_row_2() argument
162 *dst++ = clr; in console_set_row_2()
171 *dst++ = clr; in console_set_row_2()
180 *dst++ = clr; in console_set_row_2()
274 static int console_set_row_3(struct udevice *dev, uint row, int clr) in console_set_row_3() argument
289 *dst++ = clr; in console_set_row_3()
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A De1000.h687 * R/clr - register is read only and is cleared when read
702 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
771 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
772 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
773 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
774 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
775 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
776 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
777 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
778 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
H A Dpic32_eth.c64 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
78 writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */ in pic32_mii_init()
84 writel(EMAC_RMII_RESET, &emac_p->supp.clr); in pic32_mii_init()
142 writel(EMAC_FULLDUP, &emac_p->cfg2.clr); in pic32_mac_adjust_link()
151 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_adjust_link()
197 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_init()
239 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
249 writel(0xffffffff, &ectl_p->irq.clr); in pic32_ctrl_reset()
252 writel(0xffffffff, &ectl_p->txst.clr); in pic32_ctrl_reset()
253 writel(0xffffffff, &ectl_p->rxst.clr); in pic32_ctrl_reset()
[all …]
/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-armada-370-xp.c91 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
93 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
176 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local
181 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu()
182 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu()
245 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
264 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
267 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
268 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
/OK3568_Linux_fs/kernel/drivers/staging/media/omap4iss/
H A Diss.h190 * @clr: bit mask to be cleared
194 u32 offset, u32 clr) in iss_reg_clr() argument
198 iss_reg_write(iss, res, offset, v & ~clr); in iss_reg_clr()
222 * @clr: bit mask to be cleared
225 * Clear the clr mask first and then set the set mask.
229 u32 offset, u32 clr, u32 set) in iss_reg_update() argument
233 iss_reg_write(iss, res, offset, (v & ~clr) | set); in iss_reg_update()
/OK3568_Linux_fs/debian/packages-patches/pcmanfm/1.3.1-1/
H A D0001-desktop-Support-outline-mode-in-paint_rubber_banding.patch27 …cairo_set_source_rgba(cr, (gdouble)clr.red/65535, (gdouble)clr.green/65536, (gdouble)clr.blue/6553…
35 gdk_cairo_set_source_color(cr, &clr);
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h776 * R/clr - register is read only and is cleared when read
802 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
917 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
918 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
919 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
920 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
921 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
922 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
923 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
924 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv50/
H A Dwndw.c127 union nv50_wndw_atom_mask clr = { in nv50_wndw_flush_clr() local
128 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), in nv50_wndw_flush_clr()
130 if (clr.sema ) wndw->func-> sema_clr(wndw); in nv50_wndw_flush_clr()
131 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); in nv50_wndw_flush_clr()
132 if (clr.xlut ) wndw->func-> xlut_clr(wndw); in nv50_wndw_flush_clr()
133 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
134 if (clr.image) wndw->func->image_clr(wndw); in nv50_wndw_flush_clr()
413 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check_lut()
428 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
501 asyw->clr.ntfy = armw->ntfy.handle != 0; in nv50_wndw_atomic_check()
[all …]
/OK3568_Linux_fs/kernel/kernel/irq/
H A Ddevres.c236 unsigned int clr; member
244 irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); in devm_irq_remove_generic_chip()
255 * @clr: IRQ_* bits to clear
264 unsigned int clr, unsigned int set) in devm_irq_setup_generic_chip() argument
273 irq_setup_generic_chip(gc, msk, flags, clr, set); in devm_irq_setup_generic_chip()
277 dr->clr = clr; in devm_irq_setup_generic_chip()
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Ddcr-native.h112 unsigned clr, unsigned set) in __dcri_clrset() argument
120 val = (mfdcrx(base_data) & ~clr) | set; in __dcri_clrset()
124 val = (__mfdcr(base_data) & ~clr) | set; in __dcri_clrset()
138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ argument
140 reg, clr, set)

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