Home
last modified time | relevance | path

Searched +full:2 +full:- +full:bit (Results 1 – 25 of 1304) sorted by relevance

12345678910>>...53

/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg7 # SPDX-License-Identifier: GPL-2.0+
9 # Refer doc/README.kwbimage for more details about how-to configure
12 # This configuration applies to COGE5 design (ARM-part)
13 # Two 8-Bit devices are connected on the 16-Bit bus on the same
14 # chip-select. The supported devices are
15 # MT47H256M8EB-3IT:C
16 # MT47H256M8EB-25EIT:C
22 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
23 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
24 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
H A Dkwbimage_128M16_1.cfg10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/freescale/dpaa2/
H A Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
25 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
33 DPKG_FULL_FIELD = 2
37 * enum dpkg_extract_type - Enumeration for selecting extraction type
40 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
51 * struct dpkg_mask - A structure for defining a single extraction mask
63 #define NH_FLD_ETH_DA BIT(0)
64 #define NH_FLD_ETH_SA BIT(1)
65 #define NH_FLD_ETH_LENGTH BIT(2)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/dsa/microchip/
H A Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
[all …]
H A Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #define KS_PRIO_S 2
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/rtl8188eu/include/
H A Drtl8188e_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
13 #define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */
56 * Multi-Function GPIO Pin Control.
59 * Multi-Function GPIO Select.
63 * Multi-Function control source.
117 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL + 2)
119 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL + 2)
175 /* RTL8723 series ------------------------------ */
230 #define REG_TX_RPT_TIME 0x04F0 /* 2 byte */
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/abx500/
H A Dab8500-sysctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2010
83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
[all …]
/OK3568_Linux_fs/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3308.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
22 .route_val = BIT(16 + 0) | BIT(0),
27 .func = 2,
29 .route_val = BIT(16 + 2) | BIT(16 + 3),
34 .func = 2,
36 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
41 .func = 2,
43 .route_val = BIT(16 + 4),
48 .func = 2,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/halmac/
H A Dhalmac_bit2.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /*-------------------------Modification Log-----------------------------------
7 -------------------------Modification Log-----------------------------------*/
9 /*--------------------------Include File--------------------------------------*/
11 /*--------------------------Include File--------------------------------------*/
15 1. For all bit define, it should be prefixed by "BIT_"
16 2. For all bit mask, it should be prefixed by "BIT_MASK_"
17 3. For all bit shift, it should be prefixed by "BIT_SHIFT_"
43 #define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9)
62 #define BIT_EN_WATCH_DOG_V1 BIT(8)
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Dni_tio_internal.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
17 #define GI_ARM BIT(0)
18 #define GI_SAVE_TRACE BIT(1)
19 #define GI_LOAD BIT(2)
20 #define GI_DISARM BIT(4)
23 #define GI_WRITE_SWITCH BIT(7)
24 #define GI_SYNC_GATE BIT(8)
25 #define GI_LITTLE_BIG_ENDIAN BIT(9)
26 #define GI_BANK_SWITCH_START BIT(10)
[all …]
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
24 #define NISTC_INTA_ACK_REG 2
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun50i-a64.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a64.h"
27 .enable = BIT(31),
28 .lock = BIT(28),
30 .k = _SUNXI_CCU_MULT(4, 2),
31 .m = _SUNXI_CCU_DIV(0, 2),
32 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
35 .hw.init = CLK_HW_INIT("pll-cpux",
44 * the base (2x, 4x and 8x), and one variable divider (the one true
[all …]
H A Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
34 4, 2, /* K */
35 0, 2, /* M */
36 BIT(31), /* gate */
[all …]
H A Dccu-sun8i-r40.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-r40.h"
28 .enable = BIT(31),
29 .lock = BIT(28),
31 .k = _SUNXI_CCU_MULT(4, 2),
32 .m = _SUNXI_CCU_DIV(0, 2),
33 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
36 .hw.init = CLK_HW_INIT("pll-cpu",
45 * the base (2x, 4x and 8x), and one variable divider (the one true
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Drk_codec_digital.h1 /* SPDX-License-Identifier: GPL-2.0 */
75 #define ACDCDIG_SYSCTRL0_SYNC_SEL_MASK BIT(1)
76 #define ACDCDIG_SYSCTRL0_SYNC_SEL_DAC BIT(1)
78 #define ACDCDIG_SYSCTRL0_GLB_CKE_MASK BIT(3)
79 #define ACDCDIG_SYSCTRL0_GLB_CKE_EN BIT(3)
81 #define ACDCDIG_SYSCTRL0_CLK_COM_SEL_MASK BIT(4)
82 #define ACDCDIG_SYSCTRL0_CLK_COM_SEL_DAC BIT(4)
84 #define ACDCDIG_SYSCTRL0_SYNC_MODE_MASK BIT(5)
85 #define ACDCDIG_SYSCTRL0_SYNC_MODE_SYNC BIT(5)
88 #define ACDCDIG_ADCVUCTL_ADC_BYPS_MASK BIT(2)
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/
H A Dphydm_pathdiv.c3 * Copyright(c) 2007 - 2017 Realtek Corporation.
6 * under the terms of version 2 of the GNU General Public License as
32 struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm->dm_path_div; in phydm_dtp_fix_tx_path()
35 if (path == p_dm_path_div->pre_tx_path) in phydm_dtp_fix_tx_path()
38 p_dm_path_div->pre_tx_path = path; in phydm_dtp_fix_tx_path()
40 odm_set_bb_reg(p_dm, 0x93c, BIT(18) | BIT(19), 3); in phydm_dtp_fix_tx_path()
43 if (path & BIT(i)) in phydm_dtp_fix_tx_path()
46 PHYDM_DBG(p_dm, DBG_PATH_DIV, (" number of turn-on path : (( %d ))\n", num_enable_path)); in phydm_dtp_fix_tx_path()
51 if (path == BB_PATH_A) { /* 1-1 */ in phydm_dtp_fix_tx_path()
53 odm_set_bb_reg(p_dm, 0x93c, BIT(25) | BIT(24), 0); in phydm_dtp_fix_tx_path()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
125 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
126 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
127 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
128 #define DETECT_5V_B BIT(1) /* 5V present on input B */
129 #define DETECT_5V_A BIT(0) /* 5V present on input A */
132 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
133 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
134 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/wil6210/
H A Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
H A Dtxrx_edma.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved.
32 #define WIL_RX_EDMA_ERROR_KEY (2) /* Key missing */
37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
40 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
44 #define WIL_RX_EDMA_DLPF_LU_MISS_CID_POS 2
49 #define WIL_RX_EDMA_MID_VALID_BIT BIT(20)
58 #define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_LEN 2
75 /* Enhanced Rx descriptor - MAC part
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dreset_manager_arria10.h2 * Copyright (C) 2016-2017 Intel Corporation
4 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
61 * 2 ... per1modrst
67 #define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
74 #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
75 #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
76 #define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
77 #define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
78 #define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/mac_8852b/
H A Dgpio_8852b.c6 * under the terms of version 2 of the GNU General Public License as
23 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
26 0x4F, BIT(5), BIT(5)}
29 0x66, BIT(6), BIT(6)}
32 0x4F, BIT(6), BIT(6)}
35 0x41, BIT(1), BIT(1)}
38 0x41, BIT(2), BIT(2)}
41 0x40, BIT(1) | BIT(0), BIT(0)}
44 0x40, BIT(1) | BIT(0), BIT(1)}
47 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/mac_8852b/
H A Dgpio_8852b.c6 * under the terms of version 2 of the GNU General Public License as
23 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
26 0x4F, BIT(5), BIT(5)}
29 0x66, BIT(6), BIT(6)}
32 0x4F, BIT(6), BIT(6)}
35 0x41, BIT(1), BIT(1)}
38 0x41, BIT(2), BIT(2)}
41 0x40, BIT(1) | BIT(0), BIT(0)}
44 0x40, BIT(1) | BIT(0), BIT(1)}
47 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/include/
H A Dhal_com_reg.h3 * Copyright(c) 2007 - 2017 Realtek Corporation.
6 * under the terms of version 2 of the GNU General Public License as
21 #define HAL_NAV_UPPER_UNIT 128 /* micro-second */
34 /* -----------------------------------------------------
38 * ----------------------------------------------------- */
81 #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
82 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
84 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */
112 /* -----------------------------------------------------
116 * ----------------------------------------------------- */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/include/
H A Dhal_com_reg.h3 * Copyright(c) 2007 - 2017 Realtek Corporation.
6 * under the terms of version 2 of the GNU General Public License as
21 #define HAL_NAV_UPPER_UNIT 128 /* micro-second */
34 /* -----------------------------------------------------
38 * ----------------------------------------------------- */
81 #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
82 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
84 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */
112 /* -----------------------------------------------------
116 * ----------------------------------------------------- */
[all …]

12345678910>>...53