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/OK3568_Linux_fs/kernel/drivers/of/unittest-data/
H A Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x40000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi68 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
69 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
70 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
71 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
72 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
73 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-j7200.dtsi39 #size-cells = <0>;
53 cpu0: cpu@0 {
55 reg = <0x000>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
69 reg = <0x001>;
72 i-cache-size = <0xc000>;
75 d-cache-size = <0x8000>;
85 cache-size = <0x100000>;
125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j721e.dtsi40 #size-cells = <0>;
54 cpu0: cpu@0 {
56 reg = <0x000>;
59 i-cache-size = <0xC000>;
62 d-cache-size = <0x8000>;
70 reg = <0x001>;
73 i-cache-size = <0xC000>;
76 d-cache-size = <0x8000>;
86 cache-size = <0x100000>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dat91sam9m10g45ek.h16 #define CONFIG_SYS_TEXT_BASE 0x73f00000
43 #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
56 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
79 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
82 #define CONFIG_SYS_MEMTEST_END 0x23e00000
86 #define CONFIG_ENV_OFFSET 0x120000
87 #define CONFIG_ENV_OFFSET_REDUND 0x100000
88 #define CONFIG_ENV_SIZE 0x20000
91 "nand read 0x70000000 0x200000 0x300000;" \
92 "bootm 0x70000000"
[all …]
H A Dcorvus.h27 #define CONFIG_SYS_TEXT_BASE 0x72000000
66 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
97 #define CONFIG_ENV_OFFSET 0x100000
98 #define CONFIG_ENV_OFFSET_REDUND 0x180000
102 "nand read 0x70000000 0x200000 0x300000;" \
103 "bootm 0x70000000"
113 SZ_4M, 0x1000)
117 #define CONFIG_SPL_TEXT_BASE 0x300000
129 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
130 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
[all …]
H A Dgose.h19 #define CONFIG_SYS_TEXT_BASE 0x70000000
21 #define CONFIG_SYS_TEXT_BASE 0xE6304000
26 #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
28 #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
31 #define STACK_AREA_SIZE 0xC000
36 #define RCAR_GEN2_SDRAM_BASE 0x40000000
37 #define RCAR_GEN2_SDRAM_SIZE 0x40000000
38 #define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
42 #define CONFIG_SH_ETHER_USE_PORT 0
43 #define CONFIG_SH_ETHER_PHY_ADDR 0x1
[all …]
H A Dkoelsch.h19 #define CONFIG_SYS_TEXT_BASE 0x70000000
21 #define CONFIG_SYS_TEXT_BASE 0xE6304000
26 #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
28 #define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
31 #define STACK_AREA_SIZE 0xC000
36 #define RCAR_GEN2_SDRAM_BASE 0x40000000
42 #define CONFIG_SH_ETHER_USE_PORT 0
43 #define CONFIG_SH_ETHER_PHY_ADDR 0x1
60 #define CONFIG_SYS_I2C_SLAVE 0x7F
69 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
[all …]
H A Dalt.h20 #define CONFIG_SYS_TEXT_BASE 0x70000000
22 #define CONFIG_SYS_TEXT_BASE 0xE6304000
26 #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
28 #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
30 #define STACK_AREA_SIZE 0xC000
35 #define RCAR_GEN2_SDRAM_BASE 0x40000000
44 #define CONFIG_SH_ETHER_USE_PORT 0
45 #define CONFIG_SH_ETHER_PHY_ADDR 0x1
65 #define CONFIG_SYS_I2C_SLAVE 0x7F
74 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/OK3568_Linux_fs/kernel/arch/sparc/include/asm/
H A Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-tegra/
H A Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dfbio.h13 #define FBTYPE_SUN1BW 0 /* mono */
58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)
61 int index; /* first element (0 origin) */
124 #define FB_WID_SHARED_8 0
196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
225 #define CG6_FBC 0x70000000
226 #define CG6_TEC 0x70001000
227 #define CG6_BTREGS 0x70002000
228 #define CG6_FHC 0x70004000
229 #define CG6_THC 0x70005000
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A DkuroboxHG.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x8000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A DkuroboxHD.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x4000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/OK3568_Linux_fs/kernel/include/uapi/linux/
H A Delf.h26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME 0x6474e550
39 #define PT_GNU_PROPERTY 0x6474e553
41 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
47 * or equal to PN_XNUM(0xffff), it is set to sh_info field of the
48 * section header at index 0, and PN_XNUM is set to e_phnum
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/linux/
H A Delf.h26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME 0x6474e550
40 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
46 * or equal to PN_XNUM(0xffff), it is set to sh_info field of the
47 * section header at index 0, and PN_XNUM is set to e_phnum
48 * field. Otherwise, the section header at index 0 is zero
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/linux/
H A Delf.h26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME 0x6474e550
40 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
46 * or equal to PN_XNUM(0xffff), it is set to sh_info field of the
47 * section header at index 0, and PN_XNUM is set to e_phnum
48 * field. Otherwise, the section header at index 0 is zero
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Delf.h21 #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
22 #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
23 #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
24 #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
25 #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
26 #define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */
27 #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
28 #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */
29 #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */
32 #define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/
H A Dmscc.txt25 reg = <0x71070000 0x1c>;
42 reg = <0x70000000 0x2c>;
58 reg = <0x10d0000 0x10000>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/
H A Dsharkl64.dtsi28 reg = <0 0x70000000 0 0x100>;
29 interrupts = <0 2 0xf04>;
36 reg = <0 0x70100000 0 0x100>;
37 interrupts = <0 3 0xf04>;
44 reg = <0 0x70200000 0 0x100>;
45 interrupts = <0 4 0xf04>;
52 reg = <0 0x70300000 0 0x100>;
53 interrupts = <0 5 0xf04>;
62 #clock-cells = <0>;
/OK3568_Linux_fs/kernel/drivers/net/ethernet/smsc/
H A Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
H A Dsmsc9420.h22 /* Register set is duplicated for BE at an offset of 0x200 */
23 #define LAN9420_CPSR_ENDIAN_OFFSET (0x200)
25 #define LAN9420_CPSR_ENDIAN_OFFSET (0)
28 #define PCI_VENDOR_ID_9420 (0x1055)
29 #define PCI_DEVICE_ID_9420 (0xE420)
31 #define LAN_REGISTER_EXTENT (0x400)
34 #define SMSC9420_EEPROM_MAGIC (0x9420)
41 #define BUS_MODE (0x00)
42 #define BUS_MODE_SWR_ (BIT(0))
51 #define TX_POLL_DEMAND (0x04)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Datmel-nand.txt38 device (always 0)
39 3rd entry: the memory region size (always 0x800000)
77 reg = <0x70000000 0x8000000>;
82 reg = <0xffffc070 0x490>,
83 <0xffffc500 0x100>;
91 reg = <0x10000000 0x10000000
92 0x40000000 0x30000000>;
93 ranges = <0x0 0x0 0x10000000 0x10000000
94 0x1 0x0 0x40000000 0x10000000
95 0x2 0x0 0x50000000 0x10000000
[all …]

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