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Searched +full:0 +full:x41410000 (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-r5f-rproc.yaml58 enum: [0, 1]
61 Should be either a value of 1 (LockStep mode) or 0 (Split mode),
82 either of them can be configured to appear at that R5F's address 0x0.
153 enum: [0, 1]
157 either a value of 1 (enabled) or 0 (disabled), default is disabled
162 enum: [0, 1]
166 either a value of 1 (enabled) or 0 (disabled), default is enabled if
171 enum: [0, 1]
174 address 0 (from core's view). Should be either a value of 1 (ATCM
175 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
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/OK3568_Linux_fs/kernel/arch/powerpc/kernel/
H A Dcputable.c141 .pvr_mask = 0xffff0000,
142 .pvr_value = 0x00390000,
159 .pvr_mask = 0xffff0000,
160 .pvr_value = 0x003c0000,
176 { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
177 .pvr_mask = 0xffffffff,
178 .pvr_value = 0x00440100,
195 .pvr_mask = 0xffff0000,
196 .pvr_value = 0x00440000,
213 .pvr_mask = 0xffff0000,
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/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dreg.h50 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
55 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
62 #define MSR_LE_LG 0 /* Little Endian */
77 #define MSR_SF 0
78 #define MSR_ISF 0
79 #define MSR_HV 0
80 #define MSR_S 0
88 #define MSR_SPE 0
102 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
107 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
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/OK3568_Linux_fs/u-boot/arch/x86/dts/microcode/
H A Dm0230671117.dtsi11 intel,update-revision = <0x117>;
12 intel,date-code = <0x4102013>;
13 intel,processor-signature = <0x30671>;
14 intel,checksum = <0x2abfd907>;
16 intel,processor-flags = <0x2>;
20 0x01000000 0x17010000 0x13201004 0x71060300
21 0x07d9bf2a 0x01000000 0x02000000 0xd0070100
22 0x00080100 0x00000000 0x00000000 0x00000000
23 0x00000000 0xa1000000 0x01000200 0x17010000
24 0x00000000 0x00000000 0x09041320 0x41410000
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