| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/ |
| H A D | qcom,ebi2.txt | 24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
58 ranges = <0 0x0 0x1a800000 0x00800000>,
59 <1 0x0 0x1b000000 0x00800000>,
60 <2 0x0 0x1b800000 0x00800000>,
61 <3 0x0 0x1d000000 0x08000000>,
[all …]
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| /OK3568_Linux_fs/kernel/arch/mips/cobalt/ |
| H A D | led.c | 15 .start = 0x1c000000,
16 .end = 0x1c000000,
42 return 0; in cobalt_led_add()
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| H A D | reset.c | 20 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
21 #define RESET 0x0f
28 return 0; in ledtrig_power_off_init()
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| /OK3568_Linux_fs/kernel/arch/sh/boards/ |
| H A D | board-urquell.c | 32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
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| /OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-ralink/ |
| H A D | mt7621.h | 10 #define MT7621_PALMBUS_BASE 0x1C000000
11 #define MT7621_PALMBUS_SIZE 0x03FFFFFF
13 #define MT7621_SYSC_BASE 0x1E000000
15 #define SYSC_REG_CHIP_NAME0 0x00
16 #define SYSC_REG_CHIP_NAME1 0x04
17 #define SYSC_REG_CHIP_REV 0x0c
18 #define SYSC_REG_SYSTEM_CONFIG0 0x10
19 #define SYSC_REG_SYSTEM_CONFIG1 0x14
21 #define CHIP_REV_PKG_MASK 0x1
23 #define CHIP_REV_VER_MASK 0xf
[all …]
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| /OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/goya/asic_reg/ |
| H A D | mme_masks.h | 23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
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| /OK3568_Linux_fs/kernel/arch/sh/include/cpu-sh4/cpu/ |
| H A D | addrspace.h | 10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/mediatek/ |
| H A D | mediatek,bdpsys.txt | 22 reg = <0 0x1c000000 0 0x1000>;
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/ |
| H A D | hndsoc.h | 43 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
44 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
46 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
47 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
48 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
51 #define SI_REG_BASE_SIZE 0xB000 /* size from 0xf1800000 to 0xf180AFFF (44KB) */
52 #define SI_ENUM_BASE_DEFAULT 0xF1800000 /* Enumeration space base */
53 #define SI_WRAP_BASE_DEFAULT 0xF1900000 /* Wrapper space base */
57 #define SI_ENUM_BASE_DEFAULT 0x18000000 /* Enumeration space base */
61 #define SI_WRAP_BASE_DEFAULT 0x18100000 /* Wrapper space base */
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/ |
| H A D | hndsoc.h | 43 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
44 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
46 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
47 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
48 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
51 #define SI_REG_BASE_SIZE 0xB000 /* size from 0xf1800000 to 0xf180AFFF (44KB) */
52 #define SI_ENUM_BASE_DEFAULT 0xF1800000 /* Enumeration space base */
53 #define SI_WRAP_BASE_DEFAULT 0xF1900000 /* Wrapper space base */
57 #define SI_ENUM_BASE_DEFAULT 0x18000000 /* Enumeration space base */
61 #define SI_WRAP_BASE_DEFAULT 0x18100000 /* Wrapper space base */
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/ |
| H A D | hndsoc.h | 43 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
44 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
46 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
47 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
48 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
51 #define SI_REG_BASE_SIZE 0xB000 /* size from 0xf1800000 to 0xf180AFFF (44KB) */
52 #define SI_ENUM_BASE_DEFAULT 0xF1800000 /* Enumeration space base */
53 #define SI_WRAP_BASE_DEFAULT 0xF1900000 /* Wrapper space base */
57 #define SI_ENUM_BASE_DEFAULT 0x18000000 /* Enumeration space base */
61 #define SI_WRAP_BASE_DEFAULT 0x18100000 /* Wrapper space base */
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/ |
| H A D | hndsoc.h | 42 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
43 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
45 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
46 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
47 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
49 #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
50 #define SI_WRAP_BASE 0x18100000 /* Wrapper space base */
51 #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
62 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
63 #define SI_FASTRAM_SWAPPED 0x19800000
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm/include/debug/ |
| H A D | vexpress.S | 10 #define DEBUG_LL_PHYS_BASE 0x10000000
11 #define DEBUG_LL_UART_OFFSET 0x00009000
13 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
14 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000
16 #define DEBUG_LL_UART_PHYS_CRX 0xb0090000
18 #define DEBUG_LL_VIRT_BASE 0xf8000000
27 @ should use UART at 0x10009000
29 @ at 0x1c090000
30 mrc p15, 0, \rp, c0, c0, 0
31 movw \rv, #0xc091
[all …]
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| /OK3568_Linux_fs/u-boot/arch/mips/include/asm/ |
| H A D | malta.h | 11 #define MALTA_GT_BASE 0x1be00000
12 #define MALTA_GT_PCIIO_BASE 0x18000000
13 #define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
15 #define MALTA_MSC01_BIU_BASE 0x1bc80000
16 #define MALTA_MSC01_PCI_BASE 0x1bd00000
17 #define MALTA_MSC01_PBC_BASE 0x1bd40000
18 #define MALTA_MSC01_IP1_BASE 0x1bc00000
19 #define MALTA_MSC01_IP1_SIZE 0x00400000
20 #define MALTA_MSC01_IP2_BASE1 0x10000000
21 #define MALTA_MSC01_IP2_SIZE1 0x08000000
[all …]
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| /OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-malta/ |
| H A D | spaces.h | 17 * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
18 * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
19 * 0x1c000000 - 0x1fffffff: I/O And Flash
20 * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
21 * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
23 * The kernel is still located in 0x80000000(kseg0). However,
24 * the physical mask has been shifted to 0x80000000 which exploits the alias
27 * words, the 0x80000000 virtual address maps to 0x80000000 physical address
28 * which in turn aliases to 0x0. We do this in order to be able to use a flat
29 * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
[all …]
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| /OK3568_Linux_fs/kernel/drivers/staging/mt7621-dts/ |
| H A D | gbpc2.dts | 12 memory@0 {
14 reg = <0x00000000 0x1c000000>,
15 <0x20000000 0x04000000>;
46 m25p80@0 {
50 reg = <0>;
54 partition@0 {
56 reg = <0x0 0x30000>;
62 reg = <0x30000 0x10000>;
68 reg = <0x40000 0x10000>;
74 reg = <0x50000 0x1fb0000>;
[all …]
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| H A D | gbpc1.dts | 12 memory@0 {
14 reg = <0x00000000 0x1c000000>,
15 <0x20000000 0x04000000>;
62 m25p80@0 {
66 reg = <0>;
70 partition@0 {
72 reg = <0x0 0x30000>;
78 reg = <0x30000 0x10000>;
84 reg = <0x40000 0x10000>;
90 reg = <0x50000 0x1fb0000>;
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/net/fm/ |
| H A D | ls1043.c | 12 #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
13 #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
14 #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
15 #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
16 #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
17 #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
18 #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
19 #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
20 #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
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| H A D | ls1046.c | 12 #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
13 #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
14 #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
15 #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
16 #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
17 #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
18 #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
19 #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
20 #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
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| /OK3568_Linux_fs/kernel/arch/mips/include/asm/dec/ |
| H A D | kn02xa.h | 22 #define KN02XA_SLOT_BASE 0x1c000000
27 #define KN02XA_MER 0x0c400000 /* memory error register */
28 #define KN02XA_MSR 0x0c800000 /* memory size register */
33 #define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
34 #define KN02XA_EAR 0x0e000004 /* error address register */
35 #define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
36 #define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
42 #define KN02XA_MER_RES_28 (0xf<<28) /* unused */
43 #define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */
49 #define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | arm,pl172.txt | 11 first address cell and it may accept values 0..N-1
88 Example for pl172 with nor flash on chip select 0 shown below.
92 reg = <0x40005000 0x1000>;
97 ranges = <0 0 0x1c000000 0x1000000
98 1 0 0x1d000000 0x1000000
99 2 0 0x1e000000 0x1000000
100 3 0 0x1f000000 0x1000000>;
107 mpmc,cs = <0>;
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/ |
| H A D | snps,dw-apb-ssi.yaml | 118 default: 0
124 "^.*@[0-9a-f]+$":
128 minimum: 0
157 reg = <0xfff00000 0x1000>;
159 #size-cells = <0>;
160 interrupts = <0 154 4>;
163 cs-gpios = <&gpio0 13 0>,
164 <&gpio0 14 0>;
175 reg = <0x1f040100 0x900>,
176 <0x1c000000 0x1000000>;
[all …]
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| /OK3568_Linux_fs/kernel/include/linux/bcma/ |
| H A D | bcma_regs.h | 7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
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| /OK3568_Linux_fs/kernel/arch/sh/include/mach-common/mach/ |
| H A D | urquell.h | 6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
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| /OK3568_Linux_fs/kernel/drivers/video/fbdev/vermilion/ |
| H A D | vermilion.h | 23 #define VML_DEVICE_GPU 0x5002
24 #define VML_DEVICE_VDC 0x5009
37 #define VML_R_MASK 0x3FF00000
39 #define VML_G_MASK 0x000FFC00
41 #define VML_B_MASK 0x000003FF
42 #define VML_B_SHIFT 0
45 #define VML_DSPCCNTR 0x00072180
46 #define VML_GFX_ENABLE 0x80000000
47 #define VML_GFX_GAMMABYPASS 0x40000000
48 #define VML_GFX_ARGB1555 0x0C000000
[all …]
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