1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h265e_v541"
18
19 #include <string.h>
20 #include <math.h>
21 #include <limits.h>
22
23 #include "mpp_env.h"
24 #include "mpp_mem.h"
25 #include "mpp_soc.h"
26 #include "mpp_common.h"
27 #include "mpp_device.h"
28 #include "mpp_frame_impl.h"
29
30 #include "h265e_syntax_new.h"
31 #include "hal_h265e_debug.h"
32 #include "hal_h265e_vepu541_reg.h"
33 #include "hal_h265e_vepu54x_reg_l2.h"
34 #include "vepu541_common.h"
35 #include "vepu5xx_common.h"
36 #include "rkv_enc_def.h"
37 #include "mpp_enc_hal.h"
38 #include "hal_bufs.h"
39 #include "mpp_enc_ref.h"
40
41 #define hal_h265e_err(fmt, ...) \
42 do {\
43 mpp_err_f(fmt, ## __VA_ARGS__);\
44 } while (0)
45 #define VEPU541_L2_SIZE 768
46
47 #define TILE_BUF_SIZE MPP_ALIGN(128 * 1024, 256)
48
49 typedef struct vepu541_h265_fbk_t {
50 RK_U32 hw_status; /* 0:corret, 1:error */
51 RK_U32 qp_sum;
52 RK_U32 out_strm_size;
53 RK_U32 out_hw_strm_size;
54 RK_S64 sse_sum;
55 RK_U32 st_lvl64_inter_num;
56 RK_U32 st_lvl32_inter_num;
57 RK_U32 st_lvl16_inter_num;
58 RK_U32 st_lvl8_inter_num;
59 RK_U32 st_lvl32_intra_num;
60 RK_U32 st_lvl16_intra_num;
61 RK_U32 st_lvl8_intra_num;
62 RK_U32 st_lvl4_intra_num;
63 RK_U32 st_cu_num_qp[52];
64 RK_U32 st_madp;
65 RK_U32 st_madi;
66 RK_U32 st_mb_num;
67 RK_U32 st_ctu_num;
68 } vepu541_h265_fbk;
69
70 typedef struct H265eV541HalContext_t {
71 MppEncHalApi api;
72 MppDev dev;
73 void *regs;
74 void *l2_regs;
75 void *reg_out;
76
77 vepu541_h265_fbk feedback;
78 void *dump_files;
79 RK_U32 frame_cnt_gen_ready;
80
81 RK_S32 frame_type;
82 RK_S32 last_frame_type;
83
84 /* @frame_cnt starts from ZERO */
85 RK_U32 frame_cnt;
86 Vepu541OsdCfg osd_cfg;
87 MppEncROICfg *roi_data;
88 MppEncROICfg2 *roi_data2;
89 void *roi_buf;
90 Vepu541RoiCfg *roi_buf_tmp;
91 MppBufferGroup roi_grp;
92 MppBuffer roi_hw_buf;
93 RK_U32 roi_buf_size;
94 MppBuffer qpmap;
95
96 MppEncCfgSet *cfg;
97
98 MppBufferGroup tile_grp;
99 MppBuffer hw_tile_buf[2];
100
101 RK_U32 enc_mode;
102 RK_U32 frame_size;
103 RK_S32 max_buf_cnt;
104 RK_S32 hdr_status;
105 void *input_fmt;
106 RK_U8 *src_buf;
107 RK_U8 *dst_buf;
108 RK_S32 buf_size;
109 RK_U32 frame_num;
110 HalBufs dpb_bufs;
111 RK_U32 is_vepu540;
112 RK_S32 fbc_header_len;
113 } H265eV541HalContext;
114
115 static RK_U32 klut_weight[24] = {
116 0x50800080, 0x00330000, 0xA1000100, 0x00660000, 0x42000200, 0x00CC0001,
117 0x84000400, 0x01980002, 0x08000800, 0x03300005, 0x10001000, 0x0660000A,
118 0x20002000, 0x0CC00014, 0x40004000, 0x19800028, 0x80008000, 0x33000050,
119 0x00010000, 0x660000A1, 0x00020000, 0xCC000142, 0xFF83FFFF, 0x000001FF
120 };
121
122 static RK_U32 aq_thd_default[16] = {
123 0, 0, 0, 0,
124 3, 3, 5, 5,
125 8, 8, 8, 15,
126 15, 20, 25, 35
127 };
128
129 static RK_S32 aq_qp_dealt_default[16] = {
130 -8, -7, -6, -5,
131 -4, -3, -2, -1,
132 0, 1, 2, 2,
133 3, 3, 4, 4,
134 };
135
136 static RK_U16 lvl32_intra_cst_thd[4] = {2, 6, 16, 36};
137
138 static RK_U16 lvl16_intra_cst_thd[4] = {2, 6, 16, 36};
139
140 static RK_U8 lvl32_intra_cst_wgt[8] = {23, 22, 21, 20, 22, 24, 26};
141
142 static RK_U8 lvl16_intra_cst_wgt[8] = {17, 17, 17, 18, 17, 18, 18};
143
144 static RK_U16 atr_thd[4] = {0, 0, 0, 0};
145
146 static RK_U8 lvl16_4_atr_wgt[12] = {0};
147
148 //RK_U16 atf_thd[14] = {0, 4, 0, 4, 0, 4, 0, 4, 0, 4, 16, 16, 16, 16}; /*thd 4, sad 4, wgt 6*/
149 static RK_U16 atf_thd[14] = {4, 36, 4, 36, 4, 36, 4, 36, 0, 4, 22, 22, 22, 22}; /*thd 4, sad 4, wgt 6*/
150
151 static RK_U16 atf_sad_ofst[4] = {0, 0, 0, 0};
152
153 static RK_U32 lamd_satd_qp[52] = {
154 0x00000183, 0x000001b2, 0x000001e7, 0x00000223, 0x00000266, 0x000002b1, 0x00000305, 0x00000364,
155 0x000003ce, 0x00000445, 0x000004cb, 0x00000562, 0x0000060a, 0x000006c8, 0x0000079c, 0x0000088b,
156 0x00000996, 0x00000ac3, 0x00000c14, 0x00000d8f, 0x00000f38, 0x00001115, 0x0000132d, 0x00001586,
157 0x00001829, 0x00001b1e, 0x00001e70, 0x0000222b, 0x0000265a, 0x00002b0c, 0x00003052, 0x0000363c,
158 0x00003ce1, 0x00004455, 0x00004cb4, 0x00005618, 0x000060a3, 0x00006c79, 0x000079c2, 0x000088ab,
159 0x00009967, 0x0000ac30, 0x0000c147, 0x0000d8f2, 0x0000f383, 0x00011155, 0x000132ce, 0x00015861,
160 0x0001828d, 0x0001b1e4, 0x0001e706, 0x000222ab
161 };
162
163 static RK_U32 lamd_moda_qp[52] = {
164 0x00000049, 0x0000005c, 0x00000074, 0x00000092, 0x000000b8, 0x000000e8, 0x00000124, 0x00000170,
165 0x000001cf, 0x00000248, 0x000002df, 0x0000039f, 0x0000048f, 0x000005bf, 0x0000073d, 0x0000091f,
166 0x00000b7e, 0x00000e7a, 0x0000123d, 0x000016fb, 0x00001cf4, 0x0000247b, 0x00002df6, 0x000039e9,
167 0x000048f6, 0x00005bed, 0x000073d1, 0x000091ec, 0x0000b7d9, 0x0000e7a2, 0x000123d7, 0x00016fb2,
168 0x0001cf44, 0x000247ae, 0x0002df64, 0x00039e89, 0x00048f5c, 0x0005bec8, 0x00073d12, 0x00091eb8,
169 0x000b7d90, 0x000e7a23, 0x00123d71, 0x0016fb20, 0x001cf446, 0x00247ae1, 0x002df640, 0x0039e88c,
170 0x0048f5c3, 0x005bec81, 0x0073d119, 0x0091eb85
171 };
172
173 static RK_U32 lamd_modb_qp[52] = {
174 0x00000070, 0x00000089, 0x000000b0, 0x000000e0, 0x00000112, 0x00000160, 0x000001c0, 0x00000224,
175 0x000002c0, 0x00000380, 0x00000448, 0x00000580, 0x00000700, 0x00000890, 0x00000b00, 0x00000e00,
176 0x00001120, 0x00001600, 0x00001c00, 0x00002240, 0x00002c00, 0x00003800, 0x00004480, 0x00005800,
177 0x00007000, 0x00008900, 0x0000b000, 0x0000e000, 0x00011200, 0x00016000, 0x0001c000, 0x00022400,
178 0x0002c000, 0x00038000, 0x00044800, 0x00058000, 0x00070000, 0x00089000, 0x000b0000, 0x000e0000,
179 0x00112000, 0x00160000, 0x001c0000, 0x00224000, 0x002c0000, 0x00380000, 0x00448000, 0x00580000,
180 0x00700000, 0x00890000, 0x00b00000, 0x00e00000
181 };
182
vepu54x_h265_setup_hal_bufs(H265eV541HalContext * ctx)183 static MPP_RET vepu54x_h265_setup_hal_bufs(H265eV541HalContext *ctx)
184 {
185 MPP_RET ret = MPP_OK;
186 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
187 RK_U32 frame_size;
188 Vepu541Fmt input_fmt = VEPU541_FMT_YUV420P;
189 RK_S32 mb_wd64, mb_h64;
190 MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
191 MppEncPrepCfg *prep = &ctx->cfg->prep;
192 RK_S32 old_max_cnt = ctx->max_buf_cnt;
193 RK_S32 new_max_cnt = 2;
194
195 hal_h265e_enter();
196
197 mb_wd64 = (prep->width + 63) / 64;
198 mb_h64 = (prep->height + 63) / 64 + 1;
199
200 frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
201 vepu541_set_fmt(fmt, ctx->cfg->prep.format);
202 input_fmt = (Vepu541Fmt)fmt->format;
203 switch (input_fmt) {
204 case VEPU541_FMT_YUV420P:
205 case VEPU541_FMT_YUV420SP: {
206 frame_size = frame_size * 3 / 2;
207 } break;
208 case VEPU541_FMT_YUV422P:
209 case VEPU541_FMT_YUV422SP:
210 case VEPU541_FMT_YUYV422:
211 case VEPU541_FMT_UYVY422:
212 case VEPU541_FMT_BGR565: {
213 frame_size *= 2;
214 } break;
215 case VEPU541_FMT_BGR888: {
216 frame_size *= 3;
217 } break;
218 case VEPU541_FMT_BGRA8888: {
219 frame_size *= 4;
220 } break;
221 default: {
222 hal_h265e_err("invalid src color space: %d\n", input_fmt);
223 return MPP_NOK;
224 }
225 }
226
227 if (ref_cfg) {
228 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
229 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
230 }
231
232 if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
233 size_t size[3] = {0};
234
235 hal_bufs_deinit(ctx->dpb_bufs);
236 hal_bufs_init(&ctx->dpb_bufs);
237
238 ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
239 size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
240 size[1] = (mb_wd64 * mb_h64 << 8);
241 size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256);
242 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
243
244 hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
245 ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
246
247 hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, 3, size);
248
249 ctx->frame_size = frame_size;
250 ctx->max_buf_cnt = new_max_cnt;
251 }
252 hal_h265e_leave();
253 return ret;
254 }
255
vepu540_h265_set_l2_regs(H265eV54xL2RegSet * reg)256 static void vepu540_h265_set_l2_regs(H265eV54xL2RegSet *reg)
257 {
258 reg->pre_intra_cla0_B0.pre_intra_cla0_m0 = 10;
259 reg->pre_intra_cla0_B0.pre_intra_cla0_m1 = 11;
260 reg->pre_intra_cla0_B0.pre_intra_cla0_m2 = 12;
261 reg->pre_intra_cla0_B0.pre_intra_cla0_m3 = 13;
262 reg->pre_intra_cla0_B0.pre_intra_cla0_m4 = 14;
263 reg->pre_intra_cla0_B1.pre_intra_cla0_m5 = 9;
264 reg->pre_intra_cla0_B1.pre_intra_cla0_m6 = 15;
265 reg->pre_intra_cla0_B1.pre_intra_cla0_m7 = 8;
266 reg->pre_intra_cla0_B1.pre_intra_cla0_m8 = 16;
267 reg->pre_intra_cla0_B1.pre_intra_cla0_m9 = 7;
268
269 reg->pre_intra_cla1_B0.pre_intra_cla1_m0 = 10;
270 reg->pre_intra_cla1_B0.pre_intra_cla1_m1 = 9;
271 reg->pre_intra_cla1_B0.pre_intra_cla1_m2 = 8;
272 reg->pre_intra_cla1_B0.pre_intra_cla1_m3 = 7;
273 reg->pre_intra_cla1_B0.pre_intra_cla1_m4 = 6;
274 reg->pre_intra_cla1_B1.pre_intra_cla1_m5 = 11;
275 reg->pre_intra_cla1_B1.pre_intra_cla1_m6 = 5;
276 reg->pre_intra_cla1_B1.pre_intra_cla1_m7 = 12;
277 reg->pre_intra_cla1_B1.pre_intra_cla1_m8 = 4;
278 reg->pre_intra_cla1_B1.pre_intra_cla1_m9 = 13;
279
280 reg->pre_intra_cla2_B0.pre_intra_cla2_m0 = 18;
281 reg->pre_intra_cla2_B0.pre_intra_cla2_m1 = 17;
282 reg->pre_intra_cla2_B0.pre_intra_cla2_m2 = 16;
283 reg->pre_intra_cla2_B0.pre_intra_cla2_m3 = 15;
284 reg->pre_intra_cla2_B0.pre_intra_cla2_m4 = 14;
285 reg->pre_intra_cla2_B1.pre_intra_cla2_m5 = 19;
286 reg->pre_intra_cla2_B1.pre_intra_cla2_m6 = 13;
287 reg->pre_intra_cla2_B1.pre_intra_cla2_m7 = 20;
288 reg->pre_intra_cla2_B1.pre_intra_cla2_m8 = 12;
289 reg->pre_intra_cla2_B1.pre_intra_cla2_m9 = 21;
290
291 reg->pre_intra_cla3_B0.pre_intra_cla3_m0 = 18;
292 reg->pre_intra_cla3_B0.pre_intra_cla3_m1 = 19;
293 reg->pre_intra_cla3_B0.pre_intra_cla3_m2 = 20;
294 reg->pre_intra_cla3_B0.pre_intra_cla3_m3 = 21;
295 reg->pre_intra_cla3_B0.pre_intra_cla3_m4 = 22;
296 reg->pre_intra_cla3_B1.pre_intra_cla3_m5 = 17;
297 reg->pre_intra_cla3_B1.pre_intra_cla3_m6 = 23;
298 reg->pre_intra_cla3_B1.pre_intra_cla3_m7 = 16;
299 reg->pre_intra_cla3_B1.pre_intra_cla3_m8 = 24;
300 reg->pre_intra_cla3_B1.pre_intra_cla3_m9 = 15;
301
302 reg->pre_intra_cla4_B0.pre_intra_cla4_m0 = 25;
303 reg->pre_intra_cla4_B0.pre_intra_cla4_m1 = 26;
304 reg->pre_intra_cla4_B0.pre_intra_cla4_m2 = 24;
305 reg->pre_intra_cla4_B0.pre_intra_cla4_m3 = 23;
306 reg->pre_intra_cla4_B0.pre_intra_cla4_m4 = 22;
307 reg->pre_intra_cla4_B1.pre_intra_cla4_m5 = 27;
308 reg->pre_intra_cla4_B1.pre_intra_cla4_m6 = 21;
309 reg->pre_intra_cla4_B1.pre_intra_cla4_m7 = 28;
310 reg->pre_intra_cla4_B1.pre_intra_cla4_m8 = 20;
311 reg->pre_intra_cla4_B1.pre_intra_cla4_m9 = 29;
312 ;
313 reg->pre_intra_cla5_B0.pre_intra_cla5_m0 = 27;
314 reg->pre_intra_cla5_B0.pre_intra_cla5_m1 = 26;
315 reg->pre_intra_cla5_B0.pre_intra_cla5_m2 = 28;
316 reg->pre_intra_cla5_B0.pre_intra_cla5_m3 = 29;
317 reg->pre_intra_cla5_B0.pre_intra_cla5_m4 = 30;
318 reg->pre_intra_cla5_B1.pre_intra_cla5_m5 = 25;
319 reg->pre_intra_cla5_B1.pre_intra_cla5_m6 = 31;
320 reg->pre_intra_cla5_B1.pre_intra_cla5_m7 = 24;
321 reg->pre_intra_cla5_B1.pre_intra_cla5_m8 = 32;
322 reg->pre_intra_cla5_B1.pre_intra_cla5_m9 = 23;
323 ;
324 reg->pre_intra_cla6_B0.pre_intra_cla6_m0 = 34;
325 reg->pre_intra_cla6_B0.pre_intra_cla6_m1 = 33;
326 reg->pre_intra_cla6_B0.pre_intra_cla6_m2 = 32;
327 reg->pre_intra_cla6_B0.pre_intra_cla6_m3 = 31;
328 reg->pre_intra_cla6_B0.pre_intra_cla6_m4 = 30;
329 reg->pre_intra_cla6_B1.pre_intra_cla6_m5 = 2 ;
330 reg->pre_intra_cla6_B1.pre_intra_cla6_m6 = 29;
331 reg->pre_intra_cla6_B1.pre_intra_cla6_m7 = 3 ;
332 reg->pre_intra_cla6_B1.pre_intra_cla6_m8 = 28;
333 reg->pre_intra_cla6_B1.pre_intra_cla6_m9 = 4 ;
334 ;
335 reg->pre_intra_cla7_B0.pre_intra_cla7_m0 = 34;
336 reg->pre_intra_cla7_B0.pre_intra_cla7_m1 = 2 ;
337 reg->pre_intra_cla7_B0.pre_intra_cla7_m2 = 3 ;
338 reg->pre_intra_cla7_B0.pre_intra_cla7_m3 = 4 ;
339 reg->pre_intra_cla7_B0.pre_intra_cla7_m4 = 5 ;
340 reg->pre_intra_cla7_B1.pre_intra_cla7_m5 = 33;
341 reg->pre_intra_cla7_B1.pre_intra_cla7_m6 = 6 ;
342 reg->pre_intra_cla7_B1.pre_intra_cla7_m7 = 32;
343 reg->pre_intra_cla7_B1.pre_intra_cla7_m8 = 7 ;
344 reg->pre_intra_cla7_B1.pre_intra_cla7_m9 = 31;
345 ;
346 reg->pre_intra_cla8_B0.pre_intra_cla8_m0 = 10;
347 reg->pre_intra_cla8_B0.pre_intra_cla8_m1 = 26;
348 reg->pre_intra_cla8_B0.pre_intra_cla8_m2 = 18;
349 reg->pre_intra_cla8_B0.pre_intra_cla8_m3 = 34;
350 reg->pre_intra_cla8_B0.pre_intra_cla8_m4 = 6 ;
351 reg->pre_intra_cla8_B1.pre_intra_cla8_m5 = 14;
352 reg->pre_intra_cla8_B1.pre_intra_cla8_m6 = 22;
353 reg->pre_intra_cla8_B1.pre_intra_cla8_m7 = 30;
354 reg->pre_intra_cla8_B1.pre_intra_cla8_m8 = 2 ;
355 reg->pre_intra_cla8_B1.pre_intra_cla8_m9 = 24;
356 ;
357 reg->pre_intra_cla9_B0.pre_intra_cla9_m0 = 0 ;
358 reg->pre_intra_cla9_B0.pre_intra_cla9_m1 = 0 ;
359 reg->pre_intra_cla9_B0.pre_intra_cla9_m2 = 0 ;
360 reg->pre_intra_cla9_B0.pre_intra_cla9_m3 = 0 ;
361 reg->pre_intra_cla9_B0.pre_intra_cla9_m4 = 0 ;
362 reg->pre_intra_cla9_B1.pre_intra_cla9_m5 = 0 ;
363 reg->pre_intra_cla9_B1.pre_intra_cla9_m6 = 0 ;
364 reg->pre_intra_cla9_B1.pre_intra_cla9_m7 = 0 ;
365 reg->pre_intra_cla9_B1.pre_intra_cla9_m8 = 0 ;
366 reg->pre_intra_cla9_B1.pre_intra_cla9_m9 = 0 ;
367
368 reg->pre_intra_cla10_B0.pre_intra_cla10_m0 = 0;
369 reg->pre_intra_cla10_B0.pre_intra_cla10_m1 = 0;
370 reg->pre_intra_cla10_B0.pre_intra_cla10_m2 = 0;
371 reg->pre_intra_cla10_B0.pre_intra_cla10_m3 = 0;
372 reg->pre_intra_cla10_B0.pre_intra_cla10_m4 = 0;
373 reg->pre_intra_cla10_B1.pre_intra_cla10_m5 = 0;
374 reg->pre_intra_cla10_B1.pre_intra_cla10_m6 = 0;
375 reg->pre_intra_cla10_B1.pre_intra_cla10_m7 = 0;
376 reg->pre_intra_cla10_B1.pre_intra_cla10_m8 = 0;
377 reg->pre_intra_cla10_B1.pre_intra_cla10_m9 = 0;
378
379 reg->pre_intra_cla11_B0.pre_intra_cla11_m0 = 0;
380 reg->pre_intra_cla11_B0.pre_intra_cla11_m1 = 0;
381 reg->pre_intra_cla11_B0.pre_intra_cla11_m2 = 0;
382 reg->pre_intra_cla11_B0.pre_intra_cla11_m3 = 0;
383 reg->pre_intra_cla11_B0.pre_intra_cla11_m4 = 0;
384 reg->pre_intra_cla11_B1.pre_intra_cla11_m5 = 0;
385 reg->pre_intra_cla11_B1.pre_intra_cla11_m6 = 0;
386 reg->pre_intra_cla11_B1.pre_intra_cla11_m7 = 0;
387 reg->pre_intra_cla11_B1.pre_intra_cla11_m8 = 0;
388 reg->pre_intra_cla11_B1.pre_intra_cla11_m9 = 0;
389
390 reg->pre_intra_cla12_B0.pre_intra_cla12_m0 = 0;
391 reg->pre_intra_cla12_B0.pre_intra_cla12_m1 = 0;
392 reg->pre_intra_cla12_B0.pre_intra_cla12_m2 = 0;
393 reg->pre_intra_cla12_B0.pre_intra_cla12_m3 = 0;
394 reg->pre_intra_cla12_B0.pre_intra_cla12_m4 = 0;
395 reg->pre_intra_cla12_B1.pre_intra_cla12_m5 = 0;
396 reg->pre_intra_cla12_B1.pre_intra_cla12_m6 = 0;
397 reg->pre_intra_cla12_B1.pre_intra_cla12_m7 = 0;
398 reg->pre_intra_cla12_B1.pre_intra_cla12_m8 = 0;
399 reg->pre_intra_cla12_B1.pre_intra_cla12_m9 = 0;
400
401 reg->pre_intra_cla13_B0.pre_intra_cla13_m0 = 0;
402 reg->pre_intra_cla13_B0.pre_intra_cla13_m1 = 0;
403 reg->pre_intra_cla13_B0.pre_intra_cla13_m2 = 0;
404 reg->pre_intra_cla13_B0.pre_intra_cla13_m3 = 0;
405 reg->pre_intra_cla13_B0.pre_intra_cla13_m4 = 0;
406 reg->pre_intra_cla13_B1.pre_intra_cla13_m5 = 0;
407 reg->pre_intra_cla13_B1.pre_intra_cla13_m6 = 0;
408 reg->pre_intra_cla13_B1.pre_intra_cla13_m7 = 0;
409 reg->pre_intra_cla13_B1.pre_intra_cla13_m8 = 0;
410 reg->pre_intra_cla13_B1.pre_intra_cla13_m9 = 0;
411
412 reg->pre_intra_cla14_B0.pre_intra_cla14_m0 = 0;
413 reg->pre_intra_cla14_B0.pre_intra_cla14_m1 = 0;
414 reg->pre_intra_cla14_B0.pre_intra_cla14_m2 = 0;
415 reg->pre_intra_cla14_B0.pre_intra_cla14_m3 = 0;
416 reg->pre_intra_cla14_B0.pre_intra_cla14_m4 = 0;
417 reg->pre_intra_cla14_B1.pre_intra_cla14_m5 = 0;
418 reg->pre_intra_cla14_B1.pre_intra_cla14_m6 = 0;
419 reg->pre_intra_cla14_B1.pre_intra_cla14_m7 = 0;
420 reg->pre_intra_cla14_B1.pre_intra_cla14_m8 = 0;
421 reg->pre_intra_cla14_B1.pre_intra_cla14_m9 = 0;
422
423 reg->pre_intra_cla15_B0.pre_intra_cla15_m0 = 0;
424 reg->pre_intra_cla15_B0.pre_intra_cla15_m1 = 0;
425 reg->pre_intra_cla15_B0.pre_intra_cla15_m2 = 0;
426 reg->pre_intra_cla15_B0.pre_intra_cla15_m3 = 0;
427 reg->pre_intra_cla15_B0.pre_intra_cla15_m4 = 0;
428 reg->pre_intra_cla15_B1.pre_intra_cla15_m5 = 0;
429 reg->pre_intra_cla15_B1.pre_intra_cla15_m6 = 0;
430 reg->pre_intra_cla15_B1.pre_intra_cla15_m7 = 0;
431 reg->pre_intra_cla15_B1.pre_intra_cla15_m8 = 0;
432 reg->pre_intra_cla15_B1.pre_intra_cla15_m9 = 0;
433
434 reg->pre_intra_cla16_B0.pre_intra_cla16_m0 = 0;
435 reg->pre_intra_cla16_B0.pre_intra_cla16_m1 = 0;
436 reg->pre_intra_cla16_B0.pre_intra_cla16_m2 = 0;
437 reg->pre_intra_cla16_B0.pre_intra_cla16_m3 = 0;
438 reg->pre_intra_cla16_B0.pre_intra_cla16_m4 = 0;
439 reg->pre_intra_cla16_B1.pre_intra_cla16_m5 = 0;
440 reg->pre_intra_cla16_B1.pre_intra_cla16_m6 = 0;
441 reg->pre_intra_cla16_B1.pre_intra_cla16_m7 = 0;
442 reg->pre_intra_cla16_B1.pre_intra_cla16_m8 = 0;
443 reg->pre_intra_cla16_B1.pre_intra_cla16_m9 = 0;
444
445 reg->i16_sobel_t_hevc.intra_l16_sobel_t0 = 64 ;
446 reg->i16_sobel_t_hevc.intra_l16_sobel_t1 = 200;
447 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp0 = 32 ;
448 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp1 = 32 ;
449 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp2 = 32 ;
450 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp3 = 32 ;
451 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp4 = 32 ;
452 reg->i16_sobel_a_01_hevc.intra_l16_sobel_a0_qp5 = 32 ;
453 reg->i16_sobel_a_01_hevc.intra_l16_sobel_a0_qp6 = 32 ;
454 reg->i16_sobel_a_01_hevc.intra_l16_sobel_a0_qp7 = 32 ;
455 reg->i16_sobel_a_01_hevc.intra_l16_sobel_a0_qp8 = 32 ;
456 reg->i16_sobel_b_00_hevc.intra_l16_sobel_b0_qp0 = 0 ;
457 reg->i16_sobel_b_00_hevc.intra_l16_sobel_b0_qp1 = 0 ;
458 reg->i16_sobel_b_01_hevc.intra_l16_sobel_b0_qp2 = 0 ;
459 reg->i16_sobel_b_01_hevc.intra_l16_sobel_b0_qp3 = 0 ;
460 reg->i16_sobel_b_02_hevc.intra_l16_sobel_b0_qp4 = 0 ;
461 reg->i16_sobel_b_02_hevc.intra_l16_sobel_b0_qp5 = 0 ;
462 reg->i16_sobel_b_03_hevc.intra_l16_sobel_b0_qp6 = 0 ;
463 reg->i16_sobel_b_03_hevc.intra_l16_sobel_b0_qp7 = 0 ;
464 reg->i16_sobel_b_04_hevc.intra_l16_sobel_b0_qp8 = 0 ;
465 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp0 = 13;
466 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp1 = 13;
467 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp2 = 13;
468 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp3 = 13;
469 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp4 = 13;
470 reg->i16_sobel_c_01_hevc.intra_l16_sobel_c0_qp5 = 13;
471 reg->i16_sobel_c_01_hevc.intra_l16_sobel_c0_qp6 = 13;
472 reg->i16_sobel_c_01_hevc.intra_l16_sobel_c0_qp7 = 13;
473 reg->i16_sobel_c_01_hevc.intra_l16_sobel_c0_qp8 = 13;
474 reg->i16_sobel_d_00_hevc.intra_l16_sobel_d0_qp0 = 23750;
475 reg->i16_sobel_d_00_hevc.intra_l16_sobel_d0_qp1 = 23750;
476 reg->i16_sobel_d_01_hevc.intra_l16_sobel_d0_qp2 = 23750;
477 reg->i16_sobel_d_01_hevc.intra_l16_sobel_d0_qp3 = 23750;
478 reg->i16_sobel_d_02_hevc.intra_l16_sobel_d0_qp4 = 23750;
479 reg->i16_sobel_d_02_hevc.intra_l16_sobel_d0_qp5 = 23750;
480 reg->i16_sobel_d_03_hevc.intra_l16_sobel_d0_qp6 = 23750;
481 reg->i16_sobel_d_03_hevc.intra_l16_sobel_d0_qp7 = 23750;
482 reg->i16_sobel_d_04_hevc.intra_l16_sobel_d0_qp8 = 23750;
483
484 reg->i16_sobel_e_00_17_hevc[0] = 20000;
485 reg->i16_sobel_e_00_17_hevc[2] = 20000;
486 reg->i16_sobel_e_00_17_hevc[4] = 20000;
487 reg->i16_sobel_e_00_17_hevc[6] = 20000;
488 reg->i16_sobel_e_00_17_hevc[8] = 20000;
489 reg->i16_sobel_e_00_17_hevc[10] = 20000;
490 reg->i16_sobel_e_00_17_hevc[12] = 20000;
491 reg->i16_sobel_e_00_17_hevc[14] = 20000;
492 reg->i16_sobel_e_00_17_hevc[16] = 20000;
493 reg->i16_sobel_e_00_17_hevc[1] = 0;
494 reg->i16_sobel_e_00_17_hevc[3] = 0;
495 reg->i16_sobel_e_00_17_hevc[5] = 0;
496 reg->i16_sobel_e_00_17_hevc[7] = 0;
497 reg->i16_sobel_e_00_17_hevc[9] = 0;
498 reg->i16_sobel_e_00_17_hevc[11] = 0;
499 reg->i16_sobel_e_00_17_hevc[13] = 0;
500 reg->i16_sobel_e_00_17_hevc[15] = 0;
501 reg->i16_sobel_e_00_17_hevc[17] = 0;
502
503 reg->i32_sobel_t_00_hevc.intra_l32_sobel_t2 = 640 ;
504 reg->i32_sobel_t_00_hevc.intra_l32_sobel_t3 = 0 ;
505 reg->i32_sobel_t_01_hevc.intra_l32_sobel_t4 = 8 ;
506 reg->i32_sobel_t_02_hevc.intra_l32_sobel_t5 = 100 ;
507 reg->i32_sobel_t_02_hevc.intra_l32_sobel_t6 = 100 ;
508
509 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp0 = 18;
510 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp1 = 18;
511 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp2 = 18;
512 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp3 = 18;
513 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp4 = 18;
514
515 reg->i32_sobel_b_00_hevc.intra_l32_sobel_b1_qp0 = 0;
516 reg->i32_sobel_b_00_hevc.intra_l32_sobel_b1_qp1 = 0;
517 reg->i32_sobel_b_01_hevc.intra_l32_sobel_b1_qp2 = 0;
518 reg->i32_sobel_b_01_hevc.intra_l32_sobel_b1_qp3 = 0;
519 reg->i32_sobel_b_02_hevc.intra_l32_sobel_b1_qp4 = 0;
520
521 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp0 = 18;
522 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp1 = 18;
523 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp2 = 18;
524 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp3 = 18;
525 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp4 = 18;
526
527 reg->i32_sobel_d_00_hevc.intra_l32_sobel_d1_qp0 = 0;
528 reg->i32_sobel_d_00_hevc.intra_l32_sobel_d1_qp1 = 0;
529 reg->i32_sobel_d_01_hevc.intra_l32_sobel_d1_qp2 = 0;
530 reg->i32_sobel_d_01_hevc.intra_l32_sobel_d1_qp3 = 0;
531 reg->i32_sobel_d_02_hevc.intra_l32_sobel_d1_qp4 = 0;
532
533 reg->i32_sobel_e_00_09_hevc[0] = 20000;
534 reg->i32_sobel_e_00_09_hevc[2] = 20000;
535 reg->i32_sobel_e_00_09_hevc[4] = 20000;
536 reg->i32_sobel_e_00_09_hevc[6] = 20000;
537 reg->i32_sobel_e_00_09_hevc[8] = 20000;
538
539 reg->i32_sobel_e_00_09_hevc[1] = 0;
540 reg->i32_sobel_e_00_09_hevc[3] = 0;
541 reg->i32_sobel_e_00_09_hevc[5] = 0;
542 reg->i32_sobel_e_00_09_hevc[7] = 0;
543 reg->i32_sobel_e_00_09_hevc[9] = 0;
544 }
vepu541_h265_set_l2_regs(H265eV541HalContext * ctx,H265eV54xL2RegSet * regs)545 static void vepu541_h265_set_l2_regs(H265eV541HalContext *ctx, H265eV54xL2RegSet *regs)
546 {
547 MppEncHwCfg *hw = &ctx->cfg->hw;
548 RK_U32 i;
549
550 memcpy(®s->lvl32_intra_CST_THD0, lvl32_intra_cst_thd, sizeof(lvl32_intra_cst_thd));
551 memcpy(®s->lvl16_intra_CST_THD0, lvl16_intra_cst_thd, sizeof(lvl16_intra_cst_thd));
552 memcpy(®s->lvl32_intra_CST_WGT0, lvl32_intra_cst_wgt, sizeof(lvl32_intra_cst_wgt));
553 memcpy(®s->lvl16_intra_CST_WGT0, lvl16_intra_cst_wgt, sizeof(lvl16_intra_cst_wgt));
554 regs->rdo_quant.quant_f_bias_I = 0;
555 regs->rdo_quant.quant_f_bias_P = 0;
556 memcpy(®s->atr_thd0, atr_thd, sizeof(atr_thd));
557 memcpy(®s->lvl16_atr_wgt, lvl16_4_atr_wgt, sizeof(lvl16_4_atr_wgt));
558 if (!ctx->is_vepu540) {
559 memcpy(®s->thd_541.atf_thd0, atf_thd, sizeof(atf_thd));
560 regs->thd_541.atf_thd0.atf_thd0_i32 = 0;
561 regs->thd_541.atf_thd0.atf_thd1_i32 = 63;
562 regs->thd_541.atf_thd1.atf_thd0_i16 = 0;
563 regs->thd_541.atf_thd1.atf_thd1_i16 = 63;
564 regs->thd_541.atf_sad_thd0.atf_thd0_p64 = 0;
565 regs->thd_541.atf_sad_thd0.atf_thd1_p64 = 63;
566 regs->thd_541.atf_sad_thd1.atf_thd0_p32 = 0;
567 regs->thd_541.atf_sad_thd1.atf_thd1_p32 = 63;
568 regs->thd_541.atf_sad_wgt0.atf_thd0_p16 = 0;
569 regs->thd_541.atf_sad_wgt0.atf_thd1_p16 = 63;
570 } else {
571 memcpy(®s->thd_540.atf_thd0, atf_thd, sizeof(atf_thd));
572 regs->thd_540.atf_thd0.atf_thd0_i32 = 0;
573 regs->thd_540.atf_thd0.atf_thd1_i32 = 63;
574 regs->thd_540.atf_thd1.atf_thd0_i16 = 0;
575 regs->thd_540.atf_thd1.atf_thd1_i16 = 63;
576 regs->thd_540.atf_sad_thd0.atf_thd0_p64 = 0;
577 regs->thd_540.atf_sad_thd0.atf_thd1_p64 = 63;
578 regs->thd_540.atf_sad_thd1.atf_thd0_p32 = 0;
579 regs->thd_540.atf_sad_thd1.atf_thd1_p32 = 63;
580 regs->thd_540.atf_sad_wgt0.atf_thd0_p16 = 0;
581 regs->thd_540.atf_sad_wgt0.atf_thd1_p16 = 63;
582 vepu540_h265_set_l2_regs(regs);
583 }
584 regs->atf_sad_wgt1.atf_wgt_i16 = 19;
585 regs->atf_sad_wgt1.atf_wgt_i32 = 19;
586 regs->atf_sad_wgt2.atf_wgt_p32 = 13;
587 regs->atf_sad_wgt2.atf_wgt_p64 = 13;
588 regs->atf_sad_ofst0.atf_wgt_p16 = 13;
589
590 memcpy(®s->atf_sad_ofst1, atf_sad_ofst, sizeof(atf_sad_ofst));
591 memcpy(®s->lamd_satd_qp[0], lamd_satd_qp, sizeof(lamd_satd_qp));
592 memcpy(®s->lamd_moda_qp[0], lamd_moda_qp, sizeof(lamd_moda_qp));
593 memcpy(®s->lamd_modb_qp[0], lamd_modb_qp, sizeof(lamd_modb_qp));
594
595 if (ctx->frame_type == INTRA_FRAME) {
596 RK_U8 *thd = (RK_U8 *)®s->aq_thd0;
597 RK_S8 *step = (RK_S8 *)®s->aq_qp_dlt0;
598
599 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
600 thd[i] = hw->aq_thrd_i[i];
601 step[i] = hw->aq_step_i[i] & 0x3f;
602 }
603
604 regs->rdo_quant.quant_f_bias_I = 171;
605 regs->rdo_quant.quant_f_bias_P = 85;
606 } else {
607 RK_U8 *thd = (RK_U8 *)®s->aq_thd0;
608 RK_S8 *step = (RK_S8 *)®s->aq_qp_dlt0;
609
610 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
611 thd[i] = hw->aq_thrd_p[i];
612 step[i] = hw->aq_step_p[i] & 0x3f;
613 }
614 }
615
616 MppDevRegWrCfg cfg;
617 cfg.reg = regs;
618 if (ctx->is_vepu540) {
619 cfg.size = sizeof(H265eV54xL2RegSet);
620 } else {
621 cfg.size = VEPU541_L2_SIZE ;
622 }
623 cfg.offset = VEPU541_REG_BASE_L2;
624 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
625 }
626
hal_h265e_v541_init(void * hal,MppEncHalCfg * cfg)627 MPP_RET hal_h265e_v541_init(void *hal, MppEncHalCfg *cfg)
628 {
629 MPP_RET ret = MPP_OK;
630 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
631
632 mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
633 hal_h265e_enter();
634 ctx->reg_out = mpp_calloc(H265eV541IoctlOutputElem, 1);
635 ctx->regs = mpp_calloc(H265eV541RegSet, 1);
636 ctx->l2_regs = mpp_calloc(H265eV54xL2RegSet, 1);
637 ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
638 ctx->cfg = cfg->cfg;
639 hal_bufs_init(&ctx->dpb_bufs);
640
641 ctx->frame_cnt = 0;
642 ctx->frame_cnt_gen_ready = 0;
643 ctx->enc_mode = RKV_ENC_MODE;
644 cfg->type = VPU_CLIENT_RKVENC;
645 ret = mpp_dev_init(&cfg->dev, cfg->type);
646 if (ret) {
647 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
648 return ret;
649 }
650
651 ctx->dev = cfg->dev;
652 {
653 const char *soc_name = mpp_get_soc_name();
654 if (strstr(soc_name, "rk3566") || strstr(soc_name, "rk3568")) {
655 ctx->is_vepu540 = 1;
656 }
657 }
658
659 ctx->osd_cfg.reg_base = ctx->regs;
660 ctx->osd_cfg.dev = ctx->dev;
661 ctx->osd_cfg.reg_cfg = NULL;
662 ctx->osd_cfg.plt_cfg = &ctx->cfg->plt_cfg;
663 ctx->osd_cfg.osd_data = NULL;
664 ctx->osd_cfg.osd_data2 = NULL;
665
666 ctx->frame_type = INTRA_FRAME;
667
668 { /* setup default hardware config */
669 MppEncHwCfg *hw = &cfg->cfg->hw;
670
671 hw->qp_delta_row_i = 0;
672 hw->qp_delta_row = 1;
673
674 memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
675 memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
676 memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i));
677 memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p));
678 }
679
680 hal_h265e_leave();
681 return ret;
682 }
683
hal_h265e_v541_deinit(void * hal)684 MPP_RET hal_h265e_v541_deinit(void *hal)
685 {
686 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
687 hal_h265e_enter();
688 MPP_FREE(ctx->regs);
689 MPP_FREE(ctx->l2_regs);
690 MPP_FREE(ctx->reg_out);
691 MPP_FREE(ctx->input_fmt);
692 if (ctx->roi_buf_tmp) {
693 MPP_FREE(ctx->roi_buf_tmp);
694 ctx->roi_buf_tmp = NULL;
695 }
696 if (ctx->roi_buf) {
697 mpp_buffer_put(ctx->roi_buf);
698 ctx->roi_buf = NULL;
699 }
700 hal_bufs_deinit(ctx->dpb_bufs);
701
702 if (ctx->roi_hw_buf) {
703 mpp_buffer_put(ctx->roi_hw_buf);
704 ctx->roi_hw_buf = NULL;
705 }
706 if (ctx->roi_grp) {
707 mpp_buffer_group_put(ctx->roi_grp);
708 ctx->roi_grp = NULL;
709 }
710
711 if (ctx->hw_tile_buf[0]) {
712 mpp_buffer_put(ctx->hw_tile_buf[0]);
713 ctx->hw_tile_buf[0] = NULL;
714 }
715
716 if (ctx->hw_tile_buf[1]) {
717 mpp_buffer_put(ctx->hw_tile_buf[1]);
718 ctx->hw_tile_buf[1] = NULL;
719 }
720
721 if (ctx->tile_grp) {
722 mpp_buffer_group_put(ctx->tile_grp);
723 ctx->tile_grp = NULL;
724 }
725
726 if (ctx->dev) {
727 mpp_dev_deinit(ctx->dev);
728 ctx->dev = NULL;
729 }
730 hal_h265e_leave();
731 return MPP_OK;
732 }
733
hal_h265e_vepu54x_prepare(void * hal)734 static MPP_RET hal_h265e_vepu54x_prepare(void *hal)
735 {
736 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
737 MppEncPrepCfg *prep = &ctx->cfg->prep;
738
739 hal_h265e_dbg_func("enter %p\n", hal);
740
741 if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
742 RK_S32 i;
743
744 // pre-alloc required buffers to reduce first frame delay
745 vepu54x_h265_setup_hal_bufs(ctx);
746 for (i = 0; i < ctx->max_buf_cnt; i++)
747 hal_bufs_get_buf(ctx->dpb_bufs, i);
748
749 prep->change = 0;
750 }
751
752 hal_h265e_dbg_func("leave %p\n", hal);
753
754 return MPP_OK;
755 }
756
757 static MPP_RET
vepu541_h265_set_patch_info(MppDev dev,H265eSyntax_new * syn,Vepu541Fmt input_fmt,HalEncTask * task)758 vepu541_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_fmt, HalEncTask *task)
759 {
760 MppDevRegOffsetCfg cfg_fd;
761 RK_U32 hor_stride = syn->pp.hor_stride;
762 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
763 RK_U32 frame_size = hor_stride * ver_stride;
764 RK_U32 u_offset = 0, v_offset = 0;
765 MPP_RET ret = MPP_OK;
766
767 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
768 u_offset = mpp_frame_get_fbc_offset(task->frame);
769 v_offset = 0;
770 } else {
771 switch (input_fmt) {
772 case VEPU541_FMT_YUV420P: {
773 u_offset = frame_size;
774 v_offset = frame_size * 5 / 4;
775 } break;
776 case VEPU541_FMT_YUV420SP:
777 case VEPU541_FMT_YUV422SP: {
778 u_offset = frame_size;
779 v_offset = frame_size;
780 } break;
781 case VEPU541_FMT_YUV422P: {
782 u_offset = frame_size;
783 v_offset = frame_size * 3 / 2;
784 } break;
785 case VEPU541_FMT_YUYV422:
786 case VEPU541_FMT_UYVY422: {
787 u_offset = 0;
788 v_offset = 0;
789 } break;
790 case VEPU541_FMT_BGR565:
791 case VEPU541_FMT_BGR888:
792 case VEPU541_FMT_BGRA8888: {
793 u_offset = 0;
794 v_offset = 0;
795 } break;
796 default: {
797 hal_h265e_err("unknown color space: %d\n", input_fmt);
798 u_offset = frame_size;
799 v_offset = frame_size * 5 / 4;
800 }
801 }
802 }
803
804 /* input cb addr */
805 if (u_offset) {
806 cfg_fd.reg_idx = 71;
807 cfg_fd.offset = u_offset;
808 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
809 if (ret)
810 mpp_err_f("set input cb addr offset failed %d\n", ret);
811 }
812
813 /* input cr addr */
814 if (v_offset) {
815 cfg_fd.reg_idx = 72;
816 cfg_fd.offset = v_offset;
817 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
818 if (ret)
819 mpp_err_f("set input cr addr offset failed %d\n", ret);
820 }
821
822 cfg_fd.reg_idx = 83;
823 cfg_fd.offset = mpp_buffer_get_size(task->output);
824 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
825 if (ret)
826 mpp_err_f("set output max addr offset failed %d\n", ret);
827
828 return ret;
829 }
830
vepu541_h265_set_roi(void * dst_buf,void * src_buf,RK_S32 w,RK_S32 h)831 MPP_RET vepu541_h265_set_roi(void *dst_buf, void *src_buf, RK_S32 w, RK_S32 h)
832 {
833 Vepu541RoiCfg *src = (Vepu541RoiCfg *)src_buf;
834 Vepu541RoiCfg *dst = (Vepu541RoiCfg *)dst_buf;
835 RK_S32 mb_w = MPP_ALIGN(w, 64) / 64;
836 RK_S32 mb_h = MPP_ALIGN(h, 64) / 64;
837 RK_S32 ctu_line = mb_w;
838 RK_S32 i, j, cu16cnt;
839
840 for (j = 0; j < mb_h; j++) {
841 for ( i = 0; i < mb_w; i++) {
842 RK_S32 ctu_addr = j * ctu_line + i;
843 RK_S32 cu16_num_line = ctu_line * 4;
844 for ( cu16cnt = 0; cu16cnt < 16; cu16cnt++) {
845 RK_S32 cu16_x;
846 RK_S32 cu16_y;
847 RK_S32 cu16_addr_in_frame;
848 cu16_x = cu16cnt & 3;
849 cu16_y = cu16cnt / 4;
850 cu16_x += i * 4;
851 cu16_y += j * 4;
852 cu16_addr_in_frame = cu16_x + cu16_y * cu16_num_line;
853 dst[ctu_addr * 16 + cu16cnt] = src[cu16_addr_in_frame];
854 }
855 }
856 }
857 return MPP_OK;
858 }
859
setup_vepu541_intra_refresh(H265eV541RegSet * regs,H265eV541HalContext * ctx,RK_U32 refresh_idx)860 static MPP_RET setup_vepu541_intra_refresh(H265eV541RegSet *regs, H265eV541HalContext *ctx, RK_U32 refresh_idx)
861 {
862 MPP_RET ret = MPP_OK;
863 RK_U32 h = ctx->cfg->prep.height;
864 RK_U32 w = ctx->cfg->prep.width;
865 MppEncROIRegion *region = NULL;
866 RK_U32 stride_h = MPP_ALIGN(w / 16, 4);
867 RK_U32 stride_v = MPP_ALIGN(h / 16, 4);
868 RK_U32 i = 0;
869
870 hal_h265e_dbg_func("enter\n");
871
872 if (!ctx->cfg->rc.refresh_en) {
873 ret = MPP_ERR_VALUE;
874 goto RET;
875 }
876
877 if (NULL == ctx->roi_buf) {
878 RK_S32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
879
880 if (NULL == ctx->roi_grp)
881 mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
882
883 mpp_buffer_get(ctx->roi_grp, &ctx->roi_buf, roi_buf_size);
884 ctx->roi_buf_size = roi_buf_size;
885 }
886 if (NULL == ctx->roi_buf_tmp)
887 ctx->roi_buf_tmp = (Vepu541RoiCfg *)mpp_malloc(Vepu541RoiCfg, stride_h * stride_v);
888
889 mpp_assert(ctx->roi_buf);
890 mpp_assert(ctx->roi_buf_tmp);
891 RK_S32 fd = mpp_buffer_get_fd(ctx->roi_buf);
892 void *buf = ctx->roi_buf_tmp;
893 void *dst_buf = mpp_buffer_get_ptr(ctx->roi_buf);
894 Vepu541RoiCfg cfg;
895 Vepu541RoiCfg *ptr = (Vepu541RoiCfg *)buf;
896 cfg.force_intra = 0;
897 cfg.reserved = 0;
898 cfg.qp_area_idx = 0;
899 cfg.qp_area_en = 1;
900 cfg.qp_adj = 0;
901 cfg.qp_adj_mode = 0;
902
903 for (i = 0; i < stride_h * stride_v; i++, ptr++)
904 memcpy(ptr, &cfg, sizeof(cfg));
905
906 region = mpp_calloc(MppEncROIRegion, 1);
907
908 if (NULL == region) {
909 mpp_err_f("Failed to calloc for MppEncROIRegion !\n");
910 ret = MPP_ERR_MALLOC;
911 }
912
913 if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW) {
914 region->x = 0;
915 region->w = w;
916 if (refresh_idx > 0) {
917 region->y = refresh_idx * 64 * ctx->cfg->rc.refresh_num - 128;
918 region->h = 64 * ctx->cfg->rc.refresh_num + 128;
919 } else {
920 region->y = refresh_idx * 64 * ctx->cfg->rc.refresh_num;
921 region->h = 64 * ctx->cfg->rc.refresh_num;
922 }
923 regs->me_rnge.cime_srch_v = 1;
924 } else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL) {
925 region->y = 0;
926 region->h = h;
927 if (refresh_idx > 0) {
928 region->x = refresh_idx * 64 * ctx->cfg->rc.refresh_num - 128;
929 region->w = 64 * ctx->cfg->rc.refresh_num + 128;
930 } else {
931 region->x = refresh_idx * 64 * ctx->cfg->rc.refresh_num;
932 region->w = 64 * ctx->cfg->rc.refresh_num;
933 }
934 regs->me_rnge.cime_srch_h = 1;
935 }
936
937 region->intra = 1;
938 region->quality = -ctx->cfg->rc.qp_delta_ip;
939
940 region->area_map_en = 1;
941 region->qp_area_idx = 1;
942 region->abs_qp_en = 0;
943
944 regs->enc_pic.roi_en = 1;
945 regs->roi_addr_hevc = fd;
946 vepu541_set_one_roi(buf, region, w, h);
947 vepu541_h265_set_roi(dst_buf, buf, w, h);
948 mpp_free(region);
949 RET:
950 hal_h265e_dbg_func("leave, ret %d\n", ret);
951 return ret;
952 }
953
954 static MPP_RET
vepu541_h265_set_roi_regs(H265eV541HalContext * ctx,H265eV541RegSet * regs)955 vepu541_h265_set_roi_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs)
956 {
957 if (ctx->roi_data2) {
958 MppEncROICfg2 *cfg = ( MppEncROICfg2 *)ctx->roi_data2;
959
960 regs->enc_pic.roi_en = 1;
961 regs->roi_addr_hevc = mpp_buffer_get_fd(cfg->base_cfg_buf);
962 } else if (ctx->qpmap) {
963 regs->enc_pic.roi_en = 1;
964 regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->qpmap);
965 } else {
966 MppEncROICfg *cfg = (MppEncROICfg*)ctx->roi_data;
967 RK_U32 h = ctx->cfg->prep.height;
968 RK_U32 w = ctx->cfg->prep.width;
969 RK_U8 *roi_base;
970
971 if (!cfg)
972 return MPP_OK;
973
974 if (cfg->number && cfg->regions) {
975 RK_U32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
976
977 if (!ctx->roi_hw_buf || roi_buf_size != ctx->roi_buf_size) {
978 if (NULL == ctx->roi_grp)
979 mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
980 else if (roi_buf_size != ctx->roi_buf_size) {
981 if (ctx->roi_hw_buf) {
982 mpp_buffer_put(ctx->roi_hw_buf);
983 ctx->roi_hw_buf = NULL;
984 }
985 MPP_FREE(ctx->roi_buf);
986 mpp_buffer_group_clear(ctx->roi_grp);
987 }
988 mpp_assert(ctx->roi_grp);
989 if (NULL == ctx->roi_hw_buf)
990 mpp_buffer_get(ctx->roi_grp, &ctx->roi_hw_buf, roi_buf_size);
991
992 if (ctx->roi_buf == NULL)
993 ctx->roi_buf = mpp_malloc(RK_U8, roi_buf_size);
994
995 ctx->roi_buf_size = roi_buf_size;
996 }
997
998 regs->enc_pic.roi_en = 1;
999 regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->roi_hw_buf);
1000 roi_base = (RK_U8 *)mpp_buffer_get_ptr(ctx->roi_hw_buf);
1001 vepu541_set_roi(ctx->roi_buf, cfg, w, h);
1002 vepu541_h265_set_roi(roi_base, ctx->roi_buf, w, h);
1003 }
1004 }
1005
1006 return MPP_OK;
1007 }
1008
vepu541_h265_set_rc_regs(H265eV541HalContext * ctx,H265eV541RegSet * regs,HalEncTask * task)1009 static MPP_RET vepu541_h265_set_rc_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs, HalEncTask *task)
1010 {
1011 H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
1012 EncRcTaskInfo *rc_cfg = &task->rc_task->info;
1013 MppEncCfgSet *cfg = ctx->cfg;
1014 MppEncRcCfg *rc = &cfg->rc;
1015 MppEncHwCfg *hw = &cfg->hw;
1016 MppEncCodecCfg *codec = &cfg->codec;
1017 MppEncH265Cfg *h265 = &codec->h265;
1018 RK_S32 mb_wd64, mb_h64;
1019 mb_wd64 = (syn->pp.pic_width + 63) / 64;
1020 mb_h64 = (syn->pp.pic_height + 63) / 64;
1021
1022 RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd64 * mb_h64);
1023 RK_U32 ctu_target_bits;
1024 RK_S32 negative_bits_thd, positive_bits_thd;
1025
1026 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
1027 regs->enc_pic.pic_qp = rc_cfg->quality_target;
1028 regs->synt_sli1.sli_qp = rc_cfg->quality_target;
1029
1030 regs->rc_qp.rc_max_qp = rc_cfg->quality_target;
1031 regs->rc_qp.rc_min_qp = rc_cfg->quality_target;
1032 } else {
1033 if (ctu_target_bits_mul_16 >= 0x100000) {
1034 ctu_target_bits_mul_16 = 0x50000;
1035 }
1036 ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd64) >> 4;
1037 negative_bits_thd = 0 - ctu_target_bits / 5;
1038 positive_bits_thd = ctu_target_bits / 4;
1039
1040 regs->enc_pic.pic_qp = rc_cfg->quality_target;
1041 regs->synt_sli1.sli_qp = rc_cfg->quality_target;
1042 regs->rc_cfg.rc_en = 1;
1043 regs->rc_cfg.aqmode_en = 1;
1044 regs->rc_cfg.qp_mode = 1;
1045
1046 regs->rc_cfg.rc_ctu_num = mb_wd64;
1047
1048 regs->rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
1049 hw->qp_delta_row_i : hw->qp_delta_row;
1050 regs->rc_qp.rc_max_qp = rc_cfg->quality_max;
1051 regs->rc_qp.rc_min_qp = rc_cfg->quality_min;
1052 regs->rc_tgt.ctu_ebits = ctu_target_bits_mul_16;
1053
1054 regs->rc_erp0.bits_thd0 = negative_bits_thd;
1055 regs->rc_erp1.bits_thd1 = positive_bits_thd;
1056 regs->rc_erp2.bits_thd2 = positive_bits_thd;
1057 regs->rc_erp3.bits_thd3 = positive_bits_thd;
1058 regs->rc_erp4.bits_thd4 = positive_bits_thd;
1059 regs->rc_erp5.bits_thd5 = positive_bits_thd;
1060 regs->rc_erp6.bits_thd6 = positive_bits_thd;
1061 regs->rc_erp7.bits_thd7 = positive_bits_thd;
1062 regs->rc_erp8.bits_thd8 = positive_bits_thd;
1063
1064 regs->rc_adj0.qp_adjust0 = -1;
1065 regs->rc_adj0.qp_adjust1 = 0;
1066 regs->rc_adj0.qp_adjust2 = 0;
1067 regs->rc_adj0.qp_adjust3 = 0;
1068 regs->rc_adj0.qp_adjust4 = 0;
1069 regs->rc_adj1.qp_adjust5 = 0;
1070 regs->rc_adj1.qp_adjust6 = 0;
1071 regs->rc_adj1.qp_adjust7 = 0;
1072 regs->rc_adj1.qp_adjust8 = 1;
1073
1074 regs->qpmap0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
1075 regs->qpmap0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
1076 regs->qpmap0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
1077 regs->qpmap0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
1078 regs->qpmap0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;;
1079 regs->qpmap1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
1080 regs->qpmap1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;;
1081 regs->qpmap1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
1082 regs->qpmap1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;;
1083 regs->qpmap1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
1084 regs->qpmap2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;;
1085 regs->qpmap2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
1086 regs->qpmap2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;;
1087 regs->qpmap2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
1088 regs->qpmap2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;;
1089 regs->qpmap3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
1090 regs->qpmap3.qpmap_mode = h265->qpmap_mode;
1091 }
1092 if (ctx->frame_type == INTRA_FRAME) {
1093 regs->enc_pic.rdo_wgt_sel = 0;
1094 } else {
1095 regs->enc_pic.rdo_wgt_sel = 1;
1096 }
1097 return MPP_OK;
1098 }
1099
vepu541_h265_set_pp_regs(H265eV541RegSet * regs,VepuFmtCfg * fmt,MppEncPrepCfg * prep_cfg,HalEncTask * task)1100 static MPP_RET vepu541_h265_set_pp_regs(H265eV541RegSet *regs, VepuFmtCfg *fmt,
1101 MppEncPrepCfg *prep_cfg, HalEncTask *task)
1102 {
1103 RK_S32 stridey = 0;
1104 RK_S32 stridec = 0;
1105
1106 regs->dtrns_map.src_bus_edin = fmt->src_endian;
1107 regs->src_fmt.src_cfmt = fmt->format;
1108 regs->src_fmt.alpha_swap = fmt->alpha_swap;
1109 regs->src_fmt.rbuv_swap = fmt->rbuv_swap;
1110 regs->src_fmt.src_range = fmt->src_range;
1111 regs->src_proc.src_mirr = prep_cfg->mirroring > 0;
1112 regs->src_proc.src_rot = prep_cfg->rotation;
1113
1114 if (MPP_FRAME_FMT_IS_FBC(prep_cfg->format)) {
1115 stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
1116 if (!stridey)
1117 stridey = MPP_ALIGN(prep_cfg->hor_stride, 16);
1118 } else if (prep_cfg->hor_stride) {
1119 stridey = prep_cfg->hor_stride;
1120 } else {
1121 if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 )
1122 stridey = prep_cfg->width * 4;
1123 else if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGR888 )
1124 stridey = prep_cfg->width * 3;
1125 else if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGR565 ||
1126 regs->src_fmt.src_cfmt == VEPU541_FMT_YUYV422 ||
1127 regs->src_fmt.src_cfmt == VEPU541_FMT_UYVY422)
1128 stridey = prep_cfg->width * 2;
1129 }
1130
1131 stridec = (regs->src_fmt.src_cfmt == VEPU541_FMT_YUV422SP ||
1132 regs->src_fmt.src_cfmt == VEPU541_FMT_YUV420SP) ?
1133 stridey : stridey / 2;
1134
1135 if (regs->src_fmt.src_cfmt < VEPU541_FMT_NONE) {
1136 const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color);
1137
1138 hal_h265e_dbg_simple("input color range %d colorspace %d", prep_cfg->range, prep_cfg->color);
1139
1140 regs->src_udfy.wght_r2y = cfg_coeffs->_2y.r_coeff;
1141 regs->src_udfy.wght_g2y = cfg_coeffs->_2y.g_coeff;
1142 regs->src_udfy.wght_b2y = cfg_coeffs->_2y.b_coeff;
1143
1144 regs->src_udfu.wght_r2u = cfg_coeffs->_2u.r_coeff;
1145 regs->src_udfu.wght_g2u = cfg_coeffs->_2u.g_coeff;
1146 regs->src_udfu.wght_b2u = cfg_coeffs->_2u.b_coeff;
1147
1148 regs->src_udfv.wght_r2v = cfg_coeffs->_2v.r_coeff;
1149 regs->src_udfv.wght_g2v = cfg_coeffs->_2v.g_coeff;
1150 regs->src_udfv.wght_b2v = cfg_coeffs->_2v.b_coeff;
1151
1152 regs->src_udfo.ofst_y = cfg_coeffs->_2y.offset;
1153 regs->src_udfo.ofst_u = cfg_coeffs->_2u.offset;
1154 regs->src_udfo.ofst_v = cfg_coeffs->_2v.offset;
1155
1156 hal_h265e_dbg_simple("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
1157 }
1158
1159 regs->src_strid.src_ystrid = stridey;
1160 regs->src_strid.src_cstrid = stridec;
1161
1162 return MPP_OK;
1163 }
1164
vepu541_h265_set_slice_regs(H265eSyntax_new * syn,H265eV541RegSet * regs)1165 static void vepu541_h265_set_slice_regs(H265eSyntax_new *syn, H265eV541RegSet *regs)
1166 {
1167 regs->synt_sps.smpl_adpt_ofst_en = syn->pp.sample_adaptive_offset_enabled_flag;//slice->m_sps->m_bUseSAO;
1168 regs->synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets;
1169 regs->synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps;
1170 regs->synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag;
1171 regs->synt_sps.tmpl_mvp_en = syn->pp.sps_temporal_mvp_enabled_flag;
1172 regs->synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
1173 regs->synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag;
1174
1175 regs->synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag;
1176 regs->synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag;
1177 regs->synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits;
1178 regs->synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag;
1179 regs->synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag;
1180 regs->synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26;
1181 regs->synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag;
1182 regs->synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
1183 regs->synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag;
1184 regs->synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag;
1185 regs->synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag;
1186 regs->synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
1187 regs->synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
1188 regs->synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
1189
1190 regs->synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
1191 regs->synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;
1192 regs->synt_sli0.merge_up_flag = syn->sp.merge_up_flag;
1193 regs->synt_sli0.merge_left_flag = syn->sp.merge_left_flag;
1194 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
1195
1196 regs->synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act;
1197 regs->synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act;
1198
1199 regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
1200
1201 regs->synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg;
1202 regs->synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg;
1203 regs->synt_sli0.sli_tmprl_mvp_en = syn->sp.sli_tmprl_mvp_en;
1204 regs->enc_pic.tot_poc_num = syn->sp.tot_poc_num;
1205
1206 regs->synt_sli0.pic_out_flg = syn->sp.pic_out_flg;
1207 regs->synt_sli0.sli_type = syn->sp.slice_type;
1208 regs->synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg;
1209 regs->synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg;
1210 regs->synt_sli0.sli_pps_id = syn->sp.sli_pps_id;
1211 regs->synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic;
1212
1213
1214 regs->synt_sli1.sli_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;;
1215 regs->synt_sli1.sli_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2;
1216 regs->synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli;
1217 regs->synt_sli1.sli_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
1218 regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
1219 regs->synt_sli1.sli_cb_qp_ofst = syn->pp.pps_slice_chroma_qp_offsets_present_flag ?
1220 syn->sp.sli_cb_qp_ofst : syn->pp.pps_cb_qp_offset;
1221 regs->synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd;
1222
1223 regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
1224 regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;
1225 regs->synt_sli2_rodr.sli_poc_lsb = syn->sp.sli_poc_lsb;
1226 regs->synt_sli2_rodr.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len;
1227
1228 }
1229
vepu541_h265_set_ref_regs(H265eSyntax_new * syn,H265eV541RegSet * regs)1230 static void vepu541_h265_set_ref_regs(H265eSyntax_new *syn, H265eV541RegSet *regs)
1231 {
1232 regs->synt_ref_mark0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
1233 regs->synt_ref_mark0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
1234 regs->synt_ref_mark0.num_lt_pic = syn->sp.num_lt_pic;
1235
1236 regs->synt_ref_mark1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
1237 regs->synt_ref_mark1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
1238 regs->synt_ref_mark1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
1239 regs->synt_ref_mark1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
1240 regs->synt_ref_mark1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
1241 regs->synt_ref_mark1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
1242 regs->synt_ref_mark1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
1243 regs->synt_ref_mark1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
1244 regs->synt_ref_mark1.num_neg_pic = syn->sp.num_neg_pic;
1245 regs->synt_ref_mark1.num_pos_pic = syn->sp.num_pos_pic;
1246
1247 regs->synt_ref_mark1.used_by_s0_flg = syn->sp.used_by_s0_flg;
1248 regs->synt_ref_mark2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
1249 regs->synt_ref_mark2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
1250 regs->synt_ref_mark3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
1251 regs->synt_ref_mark3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
1252
1253 regs->synt_ref_mark4.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
1254 regs->synt_ref_mark5.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
1255 regs->synt_ref_mark4.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
1256 regs->synt_ref_mark1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
1257 regs->synt_ref_mark5.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
1258 regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
1259 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
1260
1261 return;
1262 }
vepu541_h265_set_me_regs(H265eV541HalContext * ctx,H265eSyntax_new * syn,H265eV541RegSet * regs)1263 static void vepu541_h265_set_me_regs(H265eV541HalContext *ctx, H265eSyntax_new *syn, H265eV541RegSet *regs)
1264 {
1265
1266 RK_U32 cime_w = 11, cime_h = 7;
1267 RK_S32 merangx = (cime_w + 1) * 32;
1268 RK_S32 merangy = (cime_h + 1) * 32;
1269 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6;
1270
1271 if (merangx > 384) {
1272 merangx = 384;
1273 }
1274 if (merangy > 320) {
1275 merangy = 320;
1276 }
1277
1278 if (syn->pp.pic_width < merangx + 60 || syn->pp.pic_width <= 352) {
1279 if (merangx > syn->pp.pic_width ) {
1280 merangx = syn->pp.pic_width;
1281 }
1282 merangx = merangx / 4 * 2;
1283 }
1284
1285 if (syn->pp.pic_height < merangy + 60 || syn->pp.pic_height <= 288) {
1286 if (merangy > syn->pp.pic_height) {
1287 merangy = syn->pp.pic_height;
1288 }
1289 merangy = merangy / 4 * 2;
1290 }
1291
1292 {
1293 RK_S32 merange_x = merangx / 2;
1294 RK_S32 merange_y = merangy / 2;
1295 RK_S32 mxneg = ((-(merange_x << 2)) >> 2) / 4;
1296 RK_S32 myneg = ((-(merange_y << 2)) >> 2) / 4;
1297 RK_S32 mxpos = (((merange_x << 2) - 4) >> 2) / 4;
1298 RK_S32 mypos = (((merange_y << 2) - 4) >> 2) / 4;
1299
1300 mxneg = MPP_MIN(abs(mxneg), mxpos) * 4;
1301 myneg = MPP_MIN(abs(myneg), mypos) * 4;
1302
1303 merangx = mxneg * 2;
1304 merangy = myneg * 2;
1305 }
1306 regs->me_rnge.cime_srch_h = merangx / 32;
1307 regs->me_rnge.cime_srch_v = merangy / 32;
1308
1309 regs->me_rnge.rime_srch_h = 7;
1310 regs->me_rnge.rime_srch_v = 5;
1311 regs->me_rnge.dlt_frm_num = 0x1;
1312
1313 regs->me_cnst.pmv_mdst_h = 5;
1314 regs->me_cnst.pmv_mdst_v = 5;
1315 regs->me_cnst.mv_limit = 0;
1316 regs->me_cnst.mv_num = 2;
1317
1318 if (syn->pp.sps_temporal_mvp_enabled_flag &&
1319 (ctx->frame_type != INTRA_FRAME)) {
1320 if (ctx->last_frame_type == INTRA_FRAME) {
1321 regs->me_cnst.colmv_load = 0;
1322 } else {
1323 regs->me_cnst.colmv_load = 1;
1324 }
1325 regs->me_cnst.colmv_store = 1;
1326 }
1327
1328 if (syn->pp.pic_width > 2688) {
1329 regs->me_ram.cime_rama_h = 12;
1330 } else if (syn->pp.pic_width > 2048) {
1331 regs->me_ram.cime_rama_h = 16;
1332 } else {
1333 regs->me_ram.cime_rama_h = 20;
1334 }
1335
1336 {
1337 RK_S32 swin_scope_wd16 = (regs->me_rnge.cime_srch_h + 3 + 1) / 4 * 2 + 1;
1338 RK_S32 tmpMin = (regs->me_rnge.cime_srch_v + 3) / 4 * 2 + 1;
1339 if (regs->me_ram.cime_rama_h / 4 < tmpMin) {
1340 tmpMin = regs->me_ram.cime_rama_h / 4;
1341 }
1342 regs->me_ram.cime_rama_max =
1343 (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2);
1344 }
1345 regs->me_ram.cach_l2_tag = 0x0;
1346
1347 pic_wd64 = pic_wd64 << 6;
1348
1349 if (pic_wd64 <= 512)
1350 regs->me_ram.cach_l2_tag = 0x0;
1351 else if (pic_wd64 <= 1024)
1352 regs->me_ram.cach_l2_tag = 0x1;
1353 else if (pic_wd64 <= 2048)
1354 regs->me_ram.cach_l2_tag = 0x2;
1355 else if (pic_wd64 <= 4096)
1356 regs->me_ram.cach_l2_tag = 0x3;
1357 }
1358
vepu540_h265_set_me_ram(H265eSyntax_new * syn,H265eV541RegSet * regs,RK_U32 index)1359 static void vepu540_h265_set_me_ram(H265eSyntax_new *syn, H265eV541RegSet *regs, RK_U32 index)
1360 {
1361 RK_U32 cime_w = 11, cime_h = 7;
1362 RK_U32 pic_cime_temp = 0;
1363 if (syn->pp.tiles_enabled_flag == 0) {
1364 pic_cime_temp = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64;
1365 regs->me_ram.cime_linebuf_w = pic_cime_temp / 64;
1366 } else {
1367 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6;
1368 RK_S32 tile_ctu_stax = index * pic_wd64 / (syn->pp.num_tile_columns_minus1 + 1);
1369 RK_S32 tile_ctu_endx = 0;
1370 RK_S32 cime_srch_w = regs->me_rnge.cime_srch_h;
1371
1372 if (index == syn->pp.num_tile_columns_minus1) {
1373 tile_ctu_endx = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 - 1;
1374 } else {
1375 tile_ctu_endx = (index + 1) * pic_wd64 / (syn->pp.num_tile_columns_minus1 + 1) - 1;
1376 }
1377
1378 if (tile_ctu_stax < (cime_srch_w + 3) / 4) {
1379 if (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4 > pic_wd64)
1380 pic_cime_temp = pic_wd64 * 64;
1381 else
1382 pic_cime_temp = (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4) * 64;
1383 } else {
1384 if (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4 > pic_wd64)
1385 pic_cime_temp = (pic_wd64 - tile_ctu_stax + (cime_srch_w + 3) / 4) * 64;
1386 else
1387 pic_cime_temp = (tile_ctu_endx - tile_ctu_stax + 1 + (cime_srch_w + 3) / 4 * 2) * 64;
1388 }
1389 regs->me_ram.cime_linebuf_w = pic_cime_temp / 64;
1390
1391 }
1392
1393 {
1394
1395 RK_S32 w_temp = 1296;
1396 RK_S32 h_temp = 4;
1397 RK_S32 h_val_0 = 4;
1398 RK_S32 h_val_1 = 24;
1399
1400 while ((w_temp > ((h_temp - h_val_0)*regs->me_ram.cime_linebuf_w * 4 + ((h_val_1 - h_temp) * 4 * 7)))
1401 && (h_temp < 17)) {
1402 h_temp = h_temp + h_val_0;
1403 }
1404 if (w_temp < (RK_S32)((h_temp - h_val_0)*regs->me_ram.cime_linebuf_w * 4 + ((h_val_1 - h_temp) * 4 * 7)))
1405 h_temp = h_temp - h_val_0;
1406
1407 regs->me_ram.cime_rama_h = h_temp;
1408 }
1409
1410 // calc cime_rama_max
1411 {
1412 RK_S32 pic_wd64 = pic_cime_temp / 64;
1413 RK_S32 swin_scope_wd16 = (cime_w + 3 + 1) / 4 * 2 + 1;
1414 RK_S32 tmpMin = (cime_h + 3) / 4 * 2 + 1;
1415 if (regs->me_ram.cime_rama_h / 4 < tmpMin) {
1416 tmpMin = regs->me_ram.cime_rama_h / 4;
1417 }
1418 regs->me_ram.cime_rama_max = (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2);
1419 }
1420
1421 hal_h265e_dbg_detail("cime_rama_h %d, cime_rama_max %d, cime_linebuf_w %d",
1422 regs->me_ram.cime_rama_h, regs->me_ram.cime_rama_max, regs->me_ram.cime_linebuf_w);
1423 }
vepu54x_h265_set_hw_address(H265eV541HalContext * ctx,H265eV541RegSet * regs,HalEncTask * task)1424 void vepu54x_h265_set_hw_address(H265eV541HalContext *ctx, H265eV541RegSet *regs, HalEncTask *task)
1425 {
1426 HalEncTask *enc_task = task;
1427 HalBuf *recon_buf, *ref_buf;
1428 MppBuffer md_info_buf = enc_task->md_info;
1429 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1430 MppDevRegOffsetCfg cfg_fd;
1431
1432 hal_h265e_enter();
1433
1434 regs->adr_srcy_hevc = mpp_buffer_get_fd(enc_task->input);
1435 regs->adr_srcu_hevc = regs->adr_srcy_hevc;
1436 regs->adr_srcv_hevc = regs->adr_srcy_hevc;
1437
1438 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
1439 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
1440 if (!syn->sp.non_reference_flag) {
1441 regs->rfpw_h_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[0]);
1442 regs->rfpw_b_addr_hevc = regs->rfpw_h_addr_hevc;
1443
1444 cfg_fd.reg_idx = 75;
1445 cfg_fd.offset = ctx->fbc_header_len;
1446 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
1447 }
1448
1449 regs->dspw_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[1]);
1450 regs->cmvw_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[2]);
1451 regs->rfpr_h_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[0]);
1452 regs->rfpr_b_addr_hevc = regs->rfpr_h_addr_hevc;
1453 regs->dspr_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[1]);
1454 regs->cmvr_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[2]);
1455
1456 cfg_fd.reg_idx = 77;
1457 cfg_fd.offset = ctx->fbc_header_len;
1458 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
1459
1460 if (syn->pp.tiles_enabled_flag) {
1461 if (NULL == ctx->tile_grp)
1462 mpp_buffer_group_get_internal(&ctx->tile_grp, MPP_BUFFER_TYPE_ION);
1463
1464 mpp_assert(ctx->tile_grp);
1465
1466 if (NULL == ctx->hw_tile_buf[0]) {
1467 mpp_buffer_get(ctx->tile_grp, &ctx->hw_tile_buf[0], TILE_BUF_SIZE);
1468 }
1469
1470 if (NULL == ctx->hw_tile_buf[1]) {
1471 mpp_buffer_get(ctx->tile_grp, &ctx->hw_tile_buf[1], TILE_BUF_SIZE);
1472 }
1473
1474 regs->lpfw_addr_hevc = mpp_buffer_get_fd(ctx->hw_tile_buf[0]);
1475 regs->lpfr_addr_hevc = mpp_buffer_get_fd(ctx->hw_tile_buf[1]);
1476 }
1477
1478 if (md_info_buf) {
1479 regs->enc_pic.mei_stor = 1;
1480 regs->meiw_addr_hevc = mpp_buffer_get_fd(md_info_buf);
1481 } else {
1482 regs->enc_pic.mei_stor = 0;
1483 regs->meiw_addr_hevc = 0;
1484 }
1485
1486 regs->bsbb_addr_hevc = mpp_buffer_get_fd(enc_task->output);
1487 /* TODO: stream size relative with syntax */
1488 regs->bsbt_addr_hevc = regs->bsbb_addr_hevc;
1489 regs->bsbr_addr_hevc = regs->bsbb_addr_hevc;
1490 regs->bsbw_addr_hevc = regs->bsbb_addr_hevc;
1491
1492 cfg_fd.reg_idx = 86;
1493 cfg_fd.offset = mpp_packet_get_length(task->packet);
1494 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
1495
1496 regs->pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
1497 regs->pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
1498 }
1499
setup_vepu541_split(H265eV541RegSet * regs,MppEncSliceSplit * cfg)1500 static void setup_vepu541_split(H265eV541RegSet *regs, MppEncSliceSplit *cfg)
1501 {
1502 hal_h265e_dbg_func("enter\n");
1503
1504 switch (cfg->split_mode) {
1505 case MPP_ENC_SPLIT_NONE : {
1506 regs->sli_spl.sli_splt = 0;
1507 regs->sli_spl.sli_splt_mode = 0;
1508 regs->sli_spl.sli_splt_cpst = 0;
1509 regs->sli_spl.sli_max_num_m1 = 0;
1510 regs->sli_spl.sli_flsh = 0;
1511 regs->sli_spl.sli_splt_cnum_m1 = 0;
1512
1513 regs->sli_spl_byte.sli_splt_byte = 0;
1514 regs->enc_pic.slen_fifo = 0;
1515 } break;
1516 case MPP_ENC_SPLIT_BY_BYTE : {
1517 regs->sli_spl.sli_splt = 1;
1518 regs->sli_spl.sli_splt_mode = 0;
1519 regs->sli_spl.sli_splt_cpst = 0;
1520 regs->sli_spl.sli_max_num_m1 = 500;
1521 regs->sli_spl.sli_flsh = 1;
1522 regs->sli_spl.sli_splt_cnum_m1 = 0;
1523
1524 regs->sli_spl_byte.sli_splt_byte = cfg->split_arg;
1525 regs->enc_pic.slen_fifo = 0;
1526 } break;
1527 case MPP_ENC_SPLIT_BY_CTU : {
1528 regs->sli_spl.sli_splt = 1;
1529 regs->sli_spl.sli_splt_mode = 1;
1530 regs->sli_spl.sli_splt_cpst = 0;
1531 regs->sli_spl.sli_max_num_m1 = 500;
1532 regs->sli_spl.sli_flsh = 1;
1533 regs->sli_spl.sli_splt_cnum_m1 = cfg->split_arg - 1;
1534
1535 regs->sli_spl_byte.sli_splt_byte = 0;
1536 regs->enc_pic.slen_fifo = 0;
1537 } break;
1538 default : {
1539 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
1540 } break;
1541 }
1542
1543 cfg->change = 0;
1544
1545 hal_h265e_dbg_func("leave\n");
1546 }
1547
hal_h265e_v541_gen_regs(void * hal,HalEncTask * task)1548 MPP_RET hal_h265e_v541_gen_regs(void *hal, HalEncTask *task)
1549 {
1550 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1551 HalEncTask *enc_task = task;
1552 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1553 H265eV541RegSet *regs = ctx->regs;
1554 RK_U32 pic_width_align8, pic_height_align8;
1555 RK_S32 pic_wd64, pic_h64;
1556 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
1557 EncFrmStatus *frm_status = &task->rc_task->frm;
1558
1559 hal_h265e_enter();
1560 pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
1561 pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
1562 pic_wd64 = (syn->pp.pic_width + 63) / 64;
1563 pic_h64 = (syn->pp.pic_height + 63) / 64;
1564
1565 hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
1566 ctx->frame_cnt, ctx->frame_type);
1567
1568
1569 memset(regs, 0, sizeof(H265eV541RegSet));
1570 regs->enc_strt.lkt_num = 0;
1571 regs->enc_strt.rkvenc_cmd = ctx->enc_mode;
1572 regs->enc_strt.enc_cke = 1;
1573 regs->enc_clr.safe_clr = 0x0;
1574
1575 regs->lkt_addr.lkt_addr = 0x0;
1576 regs->int_en.enc_done_en = 1;
1577 regs->int_en.lkt_done_en = 1;
1578 regs->int_en.sclr_done_en = 1;
1579 regs->int_en.slc_done_en = 1;
1580 regs->int_en.bsf_ovflw_en = 1;
1581 regs->int_en.brsp_ostd_en = 1;
1582 regs->int_en.wbus_err_en = 1;
1583 regs->int_en.rbus_err_en = 1;
1584 regs->int_en.wdg_en = 0;
1585
1586 regs->enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
1587 regs->enc_rsl.pic_wfill = (syn->pp.pic_width & 0x7)
1588 ? (8 - (syn->pp.pic_width & 0x7)) : 0;
1589 regs->enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
1590 regs->enc_rsl.pic_hfill = (syn->pp.pic_height & 0x7)
1591 ? (8 - (syn->pp.pic_height & 0x7)) : 0;
1592
1593 regs->enc_pic.enc_stnd = 1; //H265
1594 regs->enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered
1595 regs->enc_pic.bs_scp = 1;
1596 regs->enc_pic.node_int = 0;
1597 regs->enc_pic.log2_ctu_num = ceil(log2((double)pic_wd64 * pic_h64));
1598
1599 regs->enc_pic.rdo_wgt_sel = (ctx->frame_type == INTRA_FRAME) ? 0 : 1;
1600
1601 regs->enc_wdg.vs_load_thd = 0;
1602 regs->enc_wdg.rfp_load_thd = 0;
1603
1604 if (ctx->is_vepu540) {
1605 regs->dtrns_cfg_540.cime_dspw_orsd = (ctx->frame_type == INTER_P_FRAME);
1606 regs->dtrns_cfg_540.axi_brsp_cke = 0x0;
1607 } else {
1608 regs->dtrns_cfg_541.cime_dspw_orsd = (ctx->frame_type == INTER_P_FRAME);
1609 regs->dtrns_cfg_541.axi_brsp_cke = 0x0;
1610 }
1611
1612 regs->dtrns_map.lpfw_bus_ordr = 0x0;
1613 regs->dtrns_map.cmvw_bus_ordr = 0x0;
1614 regs->dtrns_map.dspw_bus_ordr = 0x0;
1615 regs->dtrns_map.rfpw_bus_ordr = 0x0;
1616 regs->dtrns_map.src_bus_edin = 0x0;
1617 regs->dtrns_map.meiw_bus_edin = 0x0;
1618 regs->dtrns_map.bsw_bus_edin = 0x7;
1619 regs->dtrns_map.lktr_bus_edin = 0x0;
1620 regs->dtrns_map.roir_bus_edin = 0x0;
1621 regs->dtrns_map.lktw_bus_edin = 0x0;
1622 regs->dtrns_map.afbc_bsize = 0x1;
1623
1624
1625 regs->src_proc.src_mirr = 0;
1626 regs->src_proc.src_rot = 0;
1627 regs->src_proc.txa_en = 1;
1628 regs->src_proc.afbcd_en = (MPP_FRAME_FMT_IS_FBC(syn->pp.mpp_format)) ? 1 : 0;
1629
1630 if (!ctx->is_vepu540)
1631 vepu541_h265_set_patch_info(ctx->dev, syn, (Vepu541Fmt)fmt->format, task);
1632
1633 regs->klut_ofst.chrm_kult_ofst = (ctx->frame_type == INTRA_FRAME) ? 0 : 3;
1634 memcpy(®s->klut_wgt0, &klut_weight[0], sizeof(klut_weight));
1635
1636 regs->adr_srcy_hevc = mpp_buffer_get_fd(enc_task->input);
1637 regs->adr_srcu_hevc = regs->adr_srcy_hevc;
1638 regs->adr_srcv_hevc = regs->adr_srcy_hevc;
1639
1640 setup_vepu541_split(regs, &ctx->cfg->split);
1641
1642 vepu541_h265_set_me_regs(ctx, syn, regs);
1643
1644 regs->rdo_cfg.chrm_special = 1;
1645 regs->rdo_cfg.cu_inter_en = 0xf;
1646 regs->rdo_cfg.cu_intra_en = 0xf;
1647
1648 if (syn->pp.num_long_term_ref_pics_sps) {
1649 regs->rdo_cfg.ltm_col = 0;
1650 regs->rdo_cfg.ltm_idx0l0 = 1;
1651 } else {
1652 regs->rdo_cfg.ltm_col = 0;
1653 regs->rdo_cfg.ltm_idx0l0 = 0;
1654 }
1655
1656 regs->rdo_cfg.chrm_klut_en = 1;
1657 regs->rdo_cfg.seq_scaling_matrix_present_flg = syn->pp.scaling_list_enabled_flag;
1658 {
1659 RK_U32 i_nal_type = 0;
1660
1661 /* TODO: extend syn->frame_coding_type definition */
1662 if (ctx->frame_type == INTRA_FRAME) {
1663 /* reset ref pictures */
1664 i_nal_type = NAL_IDR_W_RADL;
1665 } else if (ctx->frame_type == INTER_P_FRAME && !syn->sp.non_reference_flag) {
1666 i_nal_type = NAL_TRAIL_R;
1667 } else {
1668 i_nal_type = NAL_TRAIL_N;
1669 }
1670 regs->synt_nal.nal_unit_type = i_nal_type;
1671 }
1672 vepu54x_h265_set_hw_address(ctx, regs, task);
1673 vepu541_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep, task);
1674
1675 vepu541_h265_set_rc_regs(ctx, regs, task);
1676
1677 vepu541_h265_set_slice_regs(syn, regs);
1678
1679 vepu541_h265_set_ref_regs(syn, regs);
1680 if (ctx->is_vepu540) {
1681 vepu540_set_osd(&ctx->osd_cfg);
1682 } else {
1683 vepu541_set_osd(&ctx->osd_cfg);
1684 }
1685 /* ROI configure */
1686 vepu541_h265_set_roi_regs(ctx, regs);
1687
1688 if (frm_status->is_i_refresh)
1689 setup_vepu541_intra_refresh(regs, ctx, frm_status->seq_idx % ctx->cfg->rc.gop);
1690
1691 ctx->frame_num++;
1692
1693 hal_h265e_leave();
1694 return MPP_OK;
1695 }
hal_h265e_v540_set_uniform_tile(H265eV541RegSet * regs,H265eSyntax_new * syn,RK_U32 index)1696 void hal_h265e_v540_set_uniform_tile(H265eV541RegSet *regs, H265eSyntax_new *syn, RK_U32 index)
1697 {
1698 if (syn->pp.tiles_enabled_flag) {
1699 RK_S32 mb_w = MPP_ALIGN(syn->pp.pic_width, 64) / 64;
1700 RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64;
1701 RK_S32 tile_width = (index + 1) * mb_w / (syn->pp.num_tile_columns_minus1 + 1) -
1702 index * mb_w / (syn->pp.num_tile_columns_minus1 + 1);
1703 if (index == syn->pp.num_tile_columns_minus1) {
1704 tile_width = mb_w - index * mb_w / (syn->pp.num_tile_columns_minus1 + 1);
1705 }
1706 regs->tile_cfg.tile_width_m1 = tile_width - 1;
1707 regs->tile_cfg.tile_height_m1 = mb_h - 1;
1708 regs->rc_cfg.rc_ctu_num = tile_width;
1709 regs->tile_cfg.tile_en = syn->pp.tiles_enabled_flag;
1710 regs->tile_pos.tile_x = (index * mb_w / (syn->pp.num_tile_columns_minus1 + 1));
1711 regs->tile_pos.tile_y = 0;
1712 if (index > 0) {
1713 RK_U32 tmp = regs->lpfr_addr_hevc;
1714 regs->lpfr_addr_hevc = regs->lpfw_addr_hevc;
1715 regs->lpfw_addr_hevc = tmp;
1716 }
1717
1718 hal_h265e_dbg_detail("tile_x %d, rc_ctu_num %d, tile_width_m1 %d",
1719 regs->tile_pos.tile_x, regs->rc_cfg.rc_ctu_num,
1720 regs->tile_cfg.tile_width_m1);
1721 }
1722 }
1723
hal_h265e_v540_start(void * hal,HalEncTask * enc_task)1724 MPP_RET hal_h265e_v540_start(void *hal, HalEncTask *enc_task)
1725 {
1726 MPP_RET ret = MPP_OK;
1727 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1728 RK_U32 length = 0, k = 0;
1729 H265eV541IoctlOutputElem *reg_out = (H265eV541IoctlOutputElem *)ctx->reg_out;
1730 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1731 RK_U32 title_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1);
1732 hal_h265e_enter();
1733 RK_U32 stream_len = 0;
1734 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
1735
1736 if (enc_task->flags.err) {
1737 hal_h265e_err("enc_task->flags.err %08x, return e arly",
1738 enc_task->flags.err);
1739 return MPP_NOK;
1740 }
1741
1742 for (k = 0; k < title_num; k++) { //v540 no support link list
1743 RK_U32 i;
1744 RK_U32 *regs = (RK_U32*)ctx->regs;
1745 H265eV541RegSet *hw_regs = ctx->regs;
1746 MppDevRegWrCfg cfg;
1747 MppDevRegRdCfg cfg1;
1748
1749 vepu540_h265_set_me_ram(syn, hw_regs, k);
1750
1751 /* set input info */
1752 vepu541_h265_set_l2_regs(ctx, (H265eV54xL2RegSet*)ctx->l2_regs);
1753 vepu541_h265_set_patch_info(ctx->dev, syn, (Vepu541Fmt)fmt->format, enc_task);
1754 if (title_num > 1)
1755 hal_h265e_v540_set_uniform_tile(hw_regs, syn, k);
1756 if (k > 0) {
1757 MppDevRegOffsetCfg cfg_fd;
1758 RK_U32 offset = mpp_packet_get_length(enc_task->packet);
1759
1760 offset += stream_len;
1761 hw_regs->bsbb_addr_hevc = mpp_buffer_get_fd(enc_task->output);
1762 hw_regs->bsbw_addr_hevc = hw_regs->bsbb_addr_hevc;
1763 cfg_fd.reg_idx = 86;
1764 cfg_fd.offset = offset;
1765 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
1766
1767 cfg_fd.reg_idx = 75;
1768 cfg_fd.offset = ctx->fbc_header_len;
1769 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
1770
1771 cfg_fd.reg_idx = 77;
1772 cfg_fd.offset = ctx->fbc_header_len;
1773 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
1774 }
1775
1776 cfg.reg = ctx->regs;
1777 cfg.size = sizeof(H265eV541RegSet);
1778 cfg.offset = 0;
1779
1780 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1781 if (ret) {
1782 mpp_err_f("set register write failed %d\n", ret);
1783 break;
1784 }
1785
1786
1787 cfg1.reg = ®_out->hw_status;
1788 cfg1.size = sizeof(RK_U32);
1789 cfg1.offset = VEPU541_REG_BASE_HW_STATUS;
1790
1791 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1792 if (ret) {
1793 mpp_err_f("set register read failed %d\n", ret);
1794 break;
1795 }
1796
1797 cfg1.reg = ®_out->st_bsl;
1798 cfg1.size = sizeof(H265eV541IoctlOutputElem) - 4;
1799 cfg1.offset = VEPU541_REG_BASE_STATISTICS;
1800
1801 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1802 if (ret) {
1803 mpp_err_f("set register read failed %d\n", ret);
1804 break;
1805 }
1806 for (i = 0; i < sizeof(H265eV541RegSet) / 4; i++) {
1807 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
1808 }
1809
1810 if (k < title_num - 1) {
1811 vepu541_h265_fbk *fb = &ctx->feedback;
1812 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1813 if (ret) {
1814 mpp_err_f("send cmd failed %d\n", ret);
1815 break;
1816 }
1817 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
1818
1819 stream_len += reg_out->st_bsl.bs_lgth;
1820 fb->qp_sum += reg_out->st_sse_qp.qp_sum;
1821 fb->out_strm_size += reg_out->st_bsl.bs_lgth;
1822 fb->sse_sum += reg_out->st_sse_l32.sse_l32 +
1823 ((RK_S64)(reg_out->st_sse_qp.sse_h8 & 0xff) << 32);
1824 fb->st_madi += reg_out->st_madi;
1825 fb->st_madp += reg_out->st_madi;
1826 fb->st_mb_num += reg_out->st_mb_num;
1827 fb->st_ctu_num += reg_out->st_ctu_num;
1828
1829 if (ret) {
1830 mpp_err_f("poll cmd failed %d\n", ret);
1831 ret = MPP_ERR_VPUHW;
1832 }
1833
1834 }
1835 }
1836
1837 hal_h265e_dbg_detail("vpu client is sending %d regs", length);
1838 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1839 if (ret) {
1840 mpp_err_f("send cmd failed %d\n", ret);
1841 }
1842 hal_h265e_leave();
1843 return ret;
1844 }
1845
hal_h265e_v541_start(void * hal,HalEncTask * task)1846 MPP_RET hal_h265e_v541_start(void *hal, HalEncTask *task)
1847 {
1848 MPP_RET ret = MPP_OK;
1849 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1850 RK_U32 length = 0;
1851 HalEncTask *enc_task = task;
1852 H265eV541IoctlOutputElem *reg_out = (H265eV541IoctlOutputElem *)ctx->reg_out;
1853 RK_U32 i;
1854 RK_U32 *regs = (RK_U32*)ctx->regs;
1855 hal_h265e_enter();
1856
1857 if (enc_task->flags.err) {
1858 hal_h265e_err("enc_task->flags.err %08x, return early",
1859 enc_task->flags.err);
1860 return MPP_NOK;
1861 }
1862 vepu541_h265_set_l2_regs(ctx, (H265eV54xL2RegSet*)ctx->l2_regs);
1863
1864 do {
1865 MppDevRegWrCfg cfg;
1866
1867 cfg.reg = ctx->regs;
1868 cfg.size = sizeof(H265eV541RegSet);
1869 cfg.offset = 0;
1870
1871 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1872 if (ret) {
1873 mpp_err_f("set register write failed %d\n", ret);
1874 break;
1875 }
1876
1877 MppDevRegRdCfg cfg1;
1878
1879 cfg1.reg = ®_out->hw_status;
1880 cfg1.size = sizeof(RK_U32);
1881 cfg1.offset = VEPU541_REG_BASE_HW_STATUS;
1882
1883 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1884 if (ret) {
1885 mpp_err_f("set register read failed %d\n", ret);
1886 break;
1887 }
1888
1889 cfg1.reg = ®_out->st_bsl;
1890 cfg1.size = sizeof(H265eV541IoctlOutputElem) - 4;
1891 cfg1.offset = VEPU541_REG_BASE_STATISTICS;
1892
1893 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1894 if (ret) {
1895 mpp_err_f("set register read failed %d\n", ret);
1896 break;
1897 }
1898
1899 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1900 if (ret) {
1901 mpp_err_f("send cmd failed %d\n", ret);
1902 break;
1903 }
1904 } while (0);
1905
1906 for (i = 0; i < sizeof(H265eV541RegSet) / 4; i++) {
1907 hal_h265e_dbg_regs("set reg[%04d]: 0%08x\n", i, regs[i]);
1908 }
1909
1910 hal_h265e_dbg_detail("vpu client is sending %d regs", length);
1911 hal_h265e_leave();
1912 return ret;
1913 }
hal_h265e_v54x_start(void * hal,HalEncTask * task)1914 MPP_RET hal_h265e_v54x_start(void *hal, HalEncTask *task)
1915 {
1916 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1917 task->hw_length = 0;
1918 if (ctx->is_vepu540) {
1919 return hal_h265e_v540_start(hal, task);
1920 } else {
1921 return hal_h265e_v541_start(hal, task);
1922 }
1923 return MPP_OK;
1924 }
1925
vepu541_h265_set_feedback(H265eV541HalContext * ctx,HalEncTask * enc_task)1926 static MPP_RET vepu541_h265_set_feedback(H265eV541HalContext *ctx, HalEncTask *enc_task)
1927 {
1928 EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
1929 vepu541_h265_fbk *fb = &ctx->feedback;
1930 MppEncCfgSet *cfg = ctx->cfg;
1931 RK_S32 mb64_num = ((cfg->prep.width + 63) / 64) * ((cfg->prep.height + 63) / 64);
1932 RK_S32 mb8_num = (mb64_num << 6);
1933 RK_S32 mb4_num = (mb8_num << 2);
1934
1935 hal_h265e_enter();
1936 H265eV541IoctlOutputElem *elem = (H265eV541IoctlOutputElem *)ctx->reg_out;
1937 RK_U32 hw_status = elem->hw_status;
1938 fb->qp_sum += elem->st_sse_qp.qp_sum;
1939 fb->out_strm_size += elem->st_bsl.bs_lgth;
1940 fb->sse_sum += elem->st_sse_l32.sse_l32 +
1941 ((RK_S64)(elem->st_sse_qp.sse_h8 & 0xff) << 32);
1942
1943 fb->hw_status = hw_status;
1944 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
1945 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
1946 hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
1947
1948 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
1949 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
1950
1951 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
1952 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
1953
1954 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
1955 hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
1956
1957 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
1958 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
1959
1960 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
1961 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
1962
1963 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
1964 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
1965
1966 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
1967 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
1968
1969 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
1970 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
1971
1972 fb->st_madi += elem->st_madi;
1973 fb->st_madp += elem->st_madp;
1974 fb->st_mb_num += elem->st_mb_num;
1975 fb->st_ctu_num += elem->st_ctu_num;
1976
1977 if (fb->st_mb_num) {
1978 fb->st_madi = fb->st_madi / fb->st_mb_num;
1979 } else {
1980 fb->st_madi = 0;
1981 }
1982 if (fb->st_ctu_num) {
1983 fb->st_madp = fb->st_madp / fb->st_ctu_num;
1984 } else {
1985 fb->st_madp = 0;
1986 }
1987
1988 fb->st_lvl64_inter_num = elem->st_lvl64_inter_num;
1989 fb->st_lvl32_inter_num = elem->st_lvl32_inter_num;
1990 fb->st_lvl32_intra_num = elem->st_lvl32_intra_num;
1991 fb->st_lvl16_inter_num = elem->st_lvl16_inter_num;
1992 fb->st_lvl16_intra_num = elem->st_lvl16_intra_num;
1993 fb->st_lvl8_inter_num = elem->st_lvl8_inter_num;
1994 fb->st_lvl8_intra_num = elem->st_lvl8_intra_num;
1995 fb->st_lvl4_intra_num = elem->st_lvl4_intra_num;
1996 memcpy(&fb->st_cu_num_qp[0], &elem->st_cu_num_qp[0], sizeof(elem->st_cu_num_qp));
1997
1998 hal_rc_ret->madi = fb->st_madi;
1999 hal_rc_ret->madp = fb->st_madp;
2000 hal_rc_ret->bit_real = fb->out_strm_size * 8;
2001
2002 if (mb4_num > 0)
2003 hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
2004 (fb->st_lvl16_intra_num << 4) +
2005 (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
2006
2007 if (mb64_num > 0) {
2008 /*
2009 hal_cfg[k].inter_lv8_prop = ((fb->st_lvl8_inter_num + (fb->st_lvl16_inter_num << 2) +
2010 (fb->st_lvl32_inter_num << 4) +
2011 (fb->st_lvl64_inter_num << 6)) << 8) / mb8_num;*/
2012
2013 hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
2014 // hal_cfg[k].sse = fb->sse_sum / mb64_num;
2015 }
2016
2017 hal_h265e_leave();
2018
2019 return MPP_OK;
2020 }
2021
2022
hal_h265e_v541_wait(void * hal,HalEncTask * task)2023 MPP_RET hal_h265e_v541_wait(void *hal, HalEncTask *task)
2024 {
2025 MPP_RET ret = MPP_OK;
2026 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
2027 HalEncTask *enc_task = task;
2028 H265eV541IoctlOutputElem *elem = (H265eV541IoctlOutputElem *)ctx->reg_out;
2029 hal_h265e_enter();
2030 if (enc_task->flags.err) {
2031 hal_h265e_err("enc_task->flags.err %08x, return early",
2032 enc_task->flags.err);
2033 return MPP_NOK;
2034 }
2035 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
2036 if (ret)
2037 mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
2038
2039 hal_h265e_leave();
2040 return ret;
2041 }
2042
hal_h265e_v541_get_task(void * hal,HalEncTask * task)2043 MPP_RET hal_h265e_v541_get_task(void *hal, HalEncTask *task)
2044 {
2045 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
2046 MppFrame frame = task->frame;
2047 EncFrmStatus *frm_status = &task->rc_task->frm;
2048
2049 hal_h265e_enter();
2050
2051 if (vepu54x_h265_setup_hal_bufs(ctx)) {
2052 hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
2053 task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
2054 return MPP_ERR_MALLOC;
2055 }
2056
2057 if (!frm_status->reencode)
2058 ctx->last_frame_type = ctx->frame_type;
2059
2060 if (frm_status->is_intra) {
2061 ctx->frame_type = INTRA_FRAME;
2062 } else {
2063 ctx->frame_type = INTER_P_FRAME;
2064 }
2065 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
2066 MppMeta meta = mpp_frame_get_meta(frame);
2067
2068 mpp_meta_get_ptr_d(meta, KEY_ROI_DATA, (void **)&ctx->roi_data, NULL);
2069 mpp_meta_get_ptr_d(meta, KEY_ROI_DATA2, (void **)&ctx->roi_data2, NULL);
2070 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data, NULL);
2071 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA2, (void **)&ctx->osd_cfg.osd_data2, NULL);
2072 mpp_meta_get_buffer_d(meta, KEY_QPMAP0, &ctx->qpmap, NULL);
2073 }
2074 memset(&ctx->feedback, 0, sizeof(vepu541_h265_fbk));
2075
2076 hal_h265e_leave();
2077 return MPP_OK;
2078 }
2079
hal_h265e_v541_ret_task(void * hal,HalEncTask * task)2080 MPP_RET hal_h265e_v541_ret_task(void *hal, HalEncTask *task)
2081 {
2082 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
2083 HalEncTask *enc_task = task;
2084 vepu541_h265_fbk *fb = &ctx->feedback;
2085 hal_h265e_enter();
2086
2087 vepu541_h265_set_feedback(ctx, enc_task);
2088
2089 enc_task->hw_length = fb->out_strm_size;
2090 enc_task->length += fb->out_strm_size;
2091
2092 hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
2093
2094 hal_h265e_leave();
2095 return MPP_OK;
2096 }
2097
2098 const MppEncHalApi hal_h265e_vepu541 = {
2099 "h265e_v541_v2",
2100 MPP_VIDEO_CodingHEVC,
2101 sizeof(H265eV541HalContext),
2102 0,
2103 hal_h265e_v541_init,
2104 hal_h265e_v541_deinit,
2105 hal_h265e_vepu54x_prepare,
2106 hal_h265e_v541_get_task,
2107 hal_h265e_v541_gen_regs,
2108 hal_h265e_v54x_start,
2109 hal_h265e_v541_wait,
2110 NULL,
2111 NULL,
2112 hal_h265e_v541_ret_task,
2113 };
2114
2115